公开(公告)号：US06194954B1

公开(公告)日：2001-02-27

申请号：US09221990

申请日：1998-12-29

Applicant: Saeng-Hwan Kim ,  Kwang-Jin Lee ,  Ki-Chang Chun

Inventor： Saeng-Hwan Kim ,  Kwang-Jin Lee ,  Ki-Chang Chun

IPC: G05F110

CPC classification number: G05F3/205 ,  H03K3/0315

Abstract: The voltage control generator for a semiconductor device is disclosed, in which the substrate bias voltage through the oscillation period of the step-up voltage generator circuit are quickly adjusted with respect to the level variation of a corresponding voltage. The circuit according to the present invention includes a control level generator generating at least one control signal for detecting a substrate bias voltage level from a substrate of a semiconductor device and adjusting the width of an oscillation period to a set level in accordance with the detected signal, a voltage control oscillator generating a signal in which the width of an oscillation period is varied to the set level in response to an output signal from the control level generator, and a charge pump supplying a stable bias voltage to the substrate of the semiconductor device by increasing or decreasing a pumping speed in response to an output signal from the voltage control oscillator. Since the voltage control oscillator is used as an oscillator for determining the pumping period of the charge pump, it is possible to effectively control the oscillation period in accordance with the detected voltage level variation for thereby decreasing the power consumption.

Abstract translation: 公开了一种用于半导体器件的电压控制发生器，其中通过升压电压发生器电路的振荡周期的衬底偏置电压相对于相应电压的电平变化被快速调节。 根据本发明的电路包括控制电平发生器，其产生用于从半导体器件的衬底检测衬底偏置电压电平的至少一个控制信号，并且根据检测到的信号将振荡周期的宽度调整到设定电平 产生振荡周期的宽度响应于来自控制电平发生器的输出信号而变化到设定电平的信号的电压控制振荡器，以及向半导体器件的衬底提供稳定的偏置电压的电荷泵 通过响应于来自电压控制振荡器的输出信号增加或减小泵送速度。 由于电压控制振荡器用作用于确定电荷泵的泵浦周期的振荡器，因此可以根据检测到的电压电平变化来有效地控制振荡周期，从而降低功耗。

公开(公告)号：US09430961B2

公开(公告)日：2016-08-30

申请号：US14172507

申请日：2014-02-04

Applicant: Chang Woon Kim ,  Kwang Jin Lee

Inventor： Chang Woon Kim ,  Kwang Jin Lee

IPC: G09G1/00 ,  G09G3/20

CPC classification number: G09G3/2003 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0291

Abstract: A data driver is disclosed. The data driver includes a first latch unit including a plurality of first latches configured to store data, a selector configured to select and/or output data in two or more first latches, a level shifter unit configured to convert a voltage level of the data in the two or more selected first latches and output the voltage level-converted data, and a second latch unit including a plurality of second latches configured to store the voltage level-converted data.

Abstract translation: 公开了一种数据驱动器。 数据驱动器包括：第一锁存单元，包括被配置为存储数据的多个第一锁存器，被配置为在两个或更多个第一锁存器中选择和/或输出数据的选择器;电平移位器单元，被配置为将数据的电压电平 两个或多个选择的第一锁存器并输出电压电平转换数据，以及第二锁存单元，包括被配置为存储电压电平转换数据的多个第二锁存器。

公开(公告)号：US09087220B2

公开(公告)日：2015-07-21

申请号：US13450578

申请日：2012-04-19

Applicant: Sang Hoan Chang ,  Kwang Jin Lee

Inventor： Sang Hoan Chang ,  Kwang Jin Lee

IPC: G06F21/79

CPC classification number: G06F21/79 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.

Abstract translation: 非易失性存储器件包括：存储单元阵列，被配置为将第一和第二多个非易失性存储器单元中的认证密钥和认证密钥配置信息与安全性要保护的数据一起存储;以及控制电路，用于控制存储器的操作 单元格阵列。

公开(公告)号：US20150109354A1

公开(公告)日：2015-04-23

申请号：US14172507

申请日：2014-02-04

Applicant: Chang Woon KIM ,  Kwang Jin LEE

Inventor： Chang Woon KIM ,  Kwang Jin LEE

IPC: G09G3/20

CPC classification number: G09G3/2003 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0291

Abstract: A data driver is disclosed. The data driver includes a first latch unit including a plurality of first latches configured to store data, a selector configured to select and/or output data in two or more first latches, a level shifter unit configured to convert a voltage level of the data in the two or more selected first latches and output the voltage level-converted data, and a second latch unit including a plurality of second latches configured to store the voltage level-converted data.

Abstract translation: 公开了一种数据驱动器。 数据驱动器包括：第一锁存单元，包括被配置为存储数据的多个第一锁存器，被配置为在两个或更多个第一锁存器中选择和/或输出数据的选择器;电平移位器单元，被配置为将数据的电压电平 两个或多个选择的第一锁存器并输出电压电平转换数据，以及第二锁存单元，包括被配置为存储电压电平转换数据的多个第二锁存器。

公开(公告)号：US08980087B2

公开(公告)日：2015-03-17

申请号：US13141277

申请日：2009-12-22

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: B01D61/18 ,  B01D61/22 ,  B01D61/20 ,  C02F1/44 ,  C02F1/00

CPC classification number: C02F1/44 ,  B01D61/18 ,  B01D61/20 ,  B01D61/22 ,  B01D65/02 ,  B01D2311/14 ,  B01D2315/06 ,  B01D2317/022 ,  B01D2317/04 ,  C02F2209/03 ,  C02F2303/20

Abstract: A system and method for filtering is disclosed, which is capable of accomplishing a filtering operation at a high recovery rate of 96% or more, and realizing a compact and simplified system structure, the system comprising a water bath including an inlet and a discharging hole, wherein feed water to be treated is supplied to the inside of the water bath through the inlet, and concentrated water is discharged out through the discharging hole; and plural membrane cassettes including first and second membrane cassettes submerged into the feed water contained in the water bath, wherein the first membrane cassette is positioned nearest to the inlet, and the second membrane cassette is positioned nearest to the discharging hole, wherein the first membrane cassette treats the feed water with a first impurity concentration; the second membrane cassette treats the feed water with a second impurity concentration; and the first impurity concentration is smaller than the second impurity concentration.

Abstract translation: 公开了一种用于过滤的系统和方法，其能够以96％以上的高回收率实现过滤操作，并且实现了紧凑且简化的系统结构，该系统包括水浴，其包括入口和排出孔 其中待处理的给水通过入口供给到水浴的内部，并且浓缩的水通过排出孔排出; 以及多个膜盒，包括浸没在所述水浴中所含的给水中的第一和第二膜盒，其中所述第一膜盒位于最靠近所述入口的位置，所述第二膜盒位于最靠近所述排出孔的位置，其中所述第一膜 盒子以第一杂质浓度处理给水; 第二膜盒处理具有第二杂质浓度的给水; 并且第一杂质浓度小于第二杂质浓度。

公开(公告)号：US08974667B2

公开(公告)日：2015-03-10

申请号：US13376124

申请日：2010-06-03

Applicant: Kwang-Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

Inventor： Kwang-Jin Lee ,  Moo-Seok Lee ,  Yong-Cheol Shin

IPC: B01D63/02

CPC classification number: B01D63/022 ,  B01D63/021 ,  B01D2313/02 ,  B01D2313/21

Abstract: A hollow fiber membrane module is disclosed, which is capable of preventing a bundle of hollow fiber membranes from being separated from a module case, the hollow fiber membrane module for accommodating a bundle of hollow fiber membranes closely held together through the use of potting agent, including a module case including: a first inner surface serving as a projection on which the bundle of hollow fiber membranes is stably placed; a second inner surface upwardly extending from one end of the first inner surface, the second inner surface including at least one separation-preventing groove to prevent the bundle of hollow fiber membranes from being separated from the module case; a third inner surface downwardly extending from the other end of the first inner surface; and a fourth inner surface connected to the third inner surface.

Abstract translation: 公开了一种中空纤维膜组件，其能够防止一束中空纤维膜与模块壳体分离，中空纤维膜组件用于容纳通过使用灌封剂紧密地保持在一起的一束中空纤维膜， 包括模块壳体，包括：第一内表面，用作其上稳定放置中空纤维膜束的突起; 从所述第一内表面的一端向上延伸的第二内表面，所述第二内表面包括至少一个分离防止槽，以防止所述中空纤维束束与所述模块壳体分离; 从所述第一内表面的另一端向下延伸的第三内表面; 以及连接到第三内表面的第四内表面。

公开(公告)号：US08713408B2

公开(公告)日：2014-04-29

申请号：US13193191

申请日：2011-07-28

Applicant: Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

Inventor： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

IPC: G11C29/00

CPC classification number: G06F11/1048

Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract translation: 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

公开(公告)号：US20130308370A1

公开(公告)日：2013-11-21

申请号：US13948138

申请日：2013-07-22

Applicant: Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

Inventor： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US20130213886A1

公开(公告)日：2013-08-22

申请号：US13876334

申请日：2011-09-27

Applicant: Kwang-Jin Lee ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Joon Yul Yang

Inventor： Kwang-Jin Lee ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Joon Yul Yang

IPC: B01D65/02

CPC classification number: B01D65/02 ,  B01D65/08 ,  B01D2313/26 ,  B01D2315/06 ,  B01D2321/185

Abstract: Disclosed are system and method for filtration which can minimize the contamination of the filtering membrane through a pretreatment and perform the pretreatment and the filtration with a filtering membrane in a single filtering unit so that any need for separate and additional space and facility for the pretreatment can be obviated. The system for filtration of the present invention comprises a fine bubble supplier for providing fine bubbles into the feed water. The pretreatment is performed by supplying the feed water to be treated into the filtering unit through a dynamic filtration layer which is formed in the filtering unit as the fine bubbles rise.

Abstract translation: 公开了用于过滤的系统和方法，其可以通过预处理来最小化过滤膜的污染，并且在单个过滤单元中用过滤膜进行预处理和过滤，使得对于预处理可能需要单独的和额外的空间和设施 被免除。 本发明的过滤系统包括用于向给水中提供细小气泡的细小气泡供应器。 通过当微细气泡上升时通过形成在过滤单元中的动态过滤层将待处理的给水供给到过滤单元中来进行预处理。

公开(公告)号：US08482994B2

公开(公告)日：2013-07-09

申请号：US13064476

申请日：2011-03-28

Applicant: Kwang-Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

Inventor： Kwang-Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

IPC: G11C11/34

CPC classification number: G11C13/0061 ,  G11C7/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract translation: 一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。