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    MANUFACTURING METHOD OF HIGH VOLTAGE SEMICONDUCTOR DEVICE
    141.
    发明公开
    MANUFACTURING METHOD OF HIGH VOLTAGE SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240154027A1

    公开(公告)日：2024-05-09

    申请号：US18413045

    申请日：2024-01-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

    Pattern decomposition method
    142.
    发明授权
    Pattern decomposition method 有权

    公开(公告)号：US11977335B2

    公开(公告)日：2024-05-07

    申请号：US17353582

    申请日：2021-06-21

    Applicant: United Microelectronics Corp.

    Inventor： Min Cheng Yang ,  Wei Cyuan Lo ,  Yung-Feng Cheng

    IPC: G03F7/00 ,  G03F1/36 ,  G03F1/70

    CPC classification number: G03F7/70466 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70475

    Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

    Static random access memory and its layout pattern
    143.
    发明公开
    Static random access memory and its layout pattern 审中-公开

    公开(公告)号：US20240147683A1

    公开(公告)日：2024-05-02

    申请号：US17994381

    申请日：2022-11-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11

    CPC classification number: H01L27/1104

    Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

    FLASH MEMORY AND MANUFACTURING METHOD THEREOF
    144.
    发明公开
    FLASH MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240138144A1

    公开(公告)日：2024-04-25

    申请号：US17994009

    申请日：2022-11-25

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Jen Yeh

    IPC: H01L29/76 ,  H01L29/423

    CPC classification number: H01L27/11553 ,  H01L29/42328

    Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    145.
    发明公开
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240136417A1

    公开(公告)日：2024-04-25

    申请号：US18395616

    申请日：2023-12-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Yu Yang

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

    Semiconductor device and method of fabricating the same
    148.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11961889B2

    公开(公告)日：2024-04-16

    申请号：US17951058

    申请日：2022-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Yu Yang

    IPC: H01L29/41 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

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