公开(公告)号：US11145380B1

公开(公告)日：2021-10-12

申请号：US16861746

申请日：2020-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Tenko Yamashita ,  Oleg Gluschenkov ,  Alexander Reznicek

IPC: H01L29/04 ,  H01L31/036 ,  G11C27/00 ,  H01L45/00 ,  G06N3/08

Abstract: Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.

公开(公告)号：US20210265345A1

公开(公告)日：2021-08-26

申请号：US16798316

申请日：2020-02-22

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Alexander Reznicek ,  Heng Wu ,  Lan Yu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/8238

Abstract: CFET devices having a gate-all-around structure are provided. In one aspect, a method of forming a CFET device includes: forming a nanosheet device stack(s) on a substrate including alternating first/second nanosheets of a first/second material, wherein lower nanosheets in the nanosheet device stack(s) are separated from the substrate and from upper nanosheets in the nanosheet device stack(s) by sacrificial nanosheets; forming a ζ-shaped dielectric spacer separating the lower and upper nanosheets; forming lower/upper source and drains on opposite sides of the lower/upper nanosheets, separated by an isolation spacer; selectively removing the first nanosheets; and forming a first gate surrounding a portion of each of the lower nanosheets including a first workfunction-setting metal(s), and a second gate surrounding a portion of each of the upper nanosheets including a second workfunction-setting metal(s), wherein the first and second workfunction-setting metals are separated by the ζ-shaped dielectric spacer. A CFET device is also provided.

公开(公告)号：US20210257543A1

公开(公告)日：2021-08-19

申请号：US16793292

申请日：2020-02-18

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Julien Frougier ,  Ruilong Xie ,  Chen Zhang

IPC: H01L43/04 ,  H01L43/14 ,  H01L43/06 ,  H01L27/22

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a first electrode upon a conductive contact of an underlying semiconductor device, forming a first vertical magnetoresistive random-access memory (MRAM) cell stack upon the first electrode, forming a spin-Hall-effect (SHE) layer above and in electrical contact with the MRAM cell stack, forming a protective dielectric layer covering a portion of the SHE layer, forming a second vertical MRAM cell stack above and in electrical contact with an exposed portion of the SHE layer, forming a second electrode above and in electrical contact with the second vertical MRAM cell stack, and forming a metal contact above and in electrical connection with the second electrode.

公开(公告)号：US20210226055A1

公开(公告)日：2021-07-22

申请号：US17225327

申请日：2021-04-08

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Gen Tsutsui ,  Lan Yu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A vertical field effect transistor structure having at least two vertically oriented fins extending from a substrate. The vertical field effect transistor structure further includes a first source/drain region disposed in the substrate between the two vertically oriented fins and under each of the fins. The outer ends of the first source/drain region are in contact with outer ends of the fins. A portion of the first source/drain region extends beyond the fins.

公开(公告)号：US11069679B2

公开(公告)日：2021-07-20

申请号：US16395563

申请日：2019-04-26

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Tenko Yamashita ,  Joshua M. Rubin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US20210217871A1

公开(公告)日：2021-07-15

申请号：US16743323

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Sung Dae Suk ,  Heng Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/78 ,  H01L27/088 ,  H01L29/08

Abstract: A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape.

公开(公告)号：US20210210633A1

公开(公告)日：2021-07-08

申请号：US16735788

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Lan Yu ,  Alexander Reznicek ,  Junli Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.

公开(公告)号：US11049940B2

公开(公告)日：2021-06-29

申请号：US16509032

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/467

Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.

公开(公告)号：US11037905B2

公开(公告)日：2021-06-15

申请号：US16395546

申请日：2019-04-26

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Gen Tsutsui ,  Tenko Yamashita

IPC: H01L25/065 ,  H01L21/762 ,  H01L25/07 ,  H01L25/00

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising a first semiconductor fin and a second VTFET stacked on the first VTFET. The second VTFET includes a second semiconductor fin that is separate and distinct from the first semiconductor fin. At least one insulating layer is disposed on a top surface of the first VTFET. The second VTFET is disposed on the at least one insulating layer. The method includes forming a first vertical VTFET on a first substrate and bonding a second substrate to and on top of the first VTFET. A second VTFET is formed on the second substrate.

公开(公告)号：US20210166754A1

公开(公告)日：2021-06-03

申请号：US17173422

申请日：2021-02-11

Applicant: International Business Machines Corporation

Inventor： Lan Yu ,  Junli Wang ,  Heng Wu ,  RUQIANG BAO ,  Dechao Guo

IPC: G11C11/412 ,  H01L27/11 ,  H01L21/84

Abstract: 6T-SRAM cell designs for larger SRAM arrays and methods of manufacture generally include a single fin device for both nFET (pass-gate (PG) and pull-down (PD)) and pFET (pull-up (PU). The pFET can be configured with a smaller effective channel width (Weff) than the nFET or with a smaller active fin height. An SRAM big cell consumes the (111) 6t-SRAM design area while provide different Weff ratios other than 1:1 for PU/PD or PU/PG as can be desired for different SRAM designs.