公开(公告)号：US10261584B2

公开(公告)日：2019-04-16

申请号：US15234141

申请日：2016-08-11

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork ,  Thomas Vogelsang

IPC: G06F3/042 ,  G06F3/01 ,  G06F1/16 ,  H04N5/247 ,  G02B5/18

Abstract: A user interface includes both a touchscreen for tactile input and one or more lensless optical sensors for sensing additional, remote gestures. Users can interact with the user interface in a volume of space near the display, and are thus not constrained to the relatively small area of the touchscreen. Remote hand or face gestures can be used to turn on or otherwise alter the tactile user interface. Shared user interfaces can operate without touch, and thus avoid cross-contamination of e.g. viruses and bacteria.

公开(公告)号：US20190082125A1

公开(公告)日：2019-03-14

申请号：US16140862

申请日：2018-09-25

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Frank Armstrong ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris ,  John Ladd ,  Michael Guidash

IPC: H04N5/355 ,  H04N5/232 ,  H04N5/235 ,  H04N5/347 ,  H04N5/3745 ,  H04N9/04 ,  H04N5/361

Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.

公开(公告)号：US10204662B2

公开(公告)日：2019-02-12

申请号：US15603333

申请日：2017-05-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US10154220B2

公开(公告)日：2018-12-11

申请号：US15563875

申请日：2016-03-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Jay Endsley ,  Michael Guidash ,  Craig M. Smith

IPC: H04N5/378 ,  H04N5/353 ,  H04N5/355 ,  H04N5/357 ,  H04N5/369 ,  H01L27/146

Abstract: Multiple image data subframes corresponding to respective portions of an exposure interval are generated within a sensor device of an image system. Depending on whether the exposure interval exceeds one or more exposure time thresholds, data representative multiple image data subframes are output from the image sensor device in one of at least two formats, including a first format in which each of the subframes of image data is output in its entirety, and a second format in which a logical combination of at least two of the subframes of image data is output instead of the at least two of the subframes of image data such that the total volume of image data output from the image sensor device is reduced relative to the first format.

公开(公告)号：US20180261266A1

公开(公告)日：2018-09-13

申请号：US15889191

申请日：2018-02-05

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US10070084B2

公开(公告)日：2018-09-04

申请号：US14989580

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374 ,  H04N5/378 ,  H04N5/365 ,  H04N5/357 ,  H04N5/376 ,  H01L27/146

Abstract: A pixel within a pixel array of an integrated-circuit image sensor outputs an analog signal representative of accumulated photocharge. First and second analog-to-digital conversions of the analog signal are initiated while the pixel is outputting the analog signal, the first analog-to-digital conversion corresponding to a low-light range of photocharge accumulation within the pixel and the second analog-to-digital conversion corresponding to a brighter-light range of photocharge accumulation within the pixel.

公开(公告)号：US09911468B2

公开(公告)日：2018-03-06

申请号：US15390674

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20170310910A1

公开(公告)日：2017-10-26

申请号：US15589149

申请日：2017-05-08

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N5/355 ,  H04N5/3745 ,  H04N5/347 ,  H01L27/146 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/3559 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H04N5/347 ,  H04N5/355 ,  H04N5/3741 ,  H04N5/37455 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

公开(公告)号：US20170195596A1

公开(公告)日：2017-07-06

申请号：US15312778

申请日：2015-05-21

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/355 ,  H04N5/235 ,  G06T7/246 ,  H04N5/232 ,  H04N5/378 ,  H04N5/343

CPC classification number: H04N5/35581 ,  G06T7/248 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/2351 ,  H04N5/343 ,  H04N5/347 ,  H04N5/37457 ,  H04N5/378 ,  H04N9/045

Abstract: In an integrated-circuit image sensor having a pixel array, a first subframe readout policy is selected from among a plurality of subframe readout policies, each of the subframe readout policies specifying a first number of subframes of image data to be readout from the pixel array for each output image frame and respective exposure durations for each of the first number of subframes of image data, wherein a shortest one of the exposure durations is uniform for each of the subframe readout policies. Each of the first number of subframes of image data is read out from the pixel array following the respective exposure durations thereof while applying a respective analog readout gain. The analog readout gain applied during readout of at least a first subframe of the first number of subframes is scaled according to a ratio of the shortest one of the exposure durations to the exposure duration of the first subframe.

公开(公告)号：US20170162252A1

公开(公告)日：2017-06-08

申请号：US15352366

申请日：2016-11-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.