公开(公告)号：US06587371B1

公开(公告)日：2003-07-01

申请号：US09944346

申请日：2001-09-04

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1114

CPC分类号： G11C11/15

摘要： Read word lines are disposed in correspondence with rows of memory cells arranged in a matrix, and bit lines and reference voltage lines are disposed in correspondence with the columns. A data read current is passed through a current path passing a selected memory cell, which is formed between a data read circuit and a read reference voltage via a data bus, a column selection gate, a bit line, and a reference voltage line. The data read circuit detects a voltage change occurring in the selected memory cell due to the data read current and outputs read data. A sum of an electric resistance value of the bit line and an electric resistance value of the reference voltage line in a portion included in the current path is set to be almost constant without depending on a row to which the selected memory cell belongs.

摘要翻译： 读取字线与排列成矩阵的存储单元的行对应配置，位线和基准电压线与列对应配置。 数据读取电流通过经由经由数据总线，列选择栅极，位线和参考电压线在数据读取电路和读取参考电压之间形成的选定存储单元的电流路径。 数据读取电路检测由于数据读取电流而在所选存储单元中发生的电压变化，并输出读取数据。 将包括在当前路径中的部分中的位线的电阻值和参考电压线的电阻值之和设置为几乎恒定，而不依赖于所选存储单元所属的行。

公开(公告)号：US06501679B2

公开(公告)日：2002-12-31

申请号：US10066558

申请日：2002-02-06

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1115

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/002

摘要： In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

摘要翻译： 在数据读取操作中，存储器单元和虚拟存储单元分别耦合到所选位线对的两个位线，并且向其提供数据读取电流。 在选择的存储单元列中，根据位线上的相应电压，读取门驱动读取数据总线对上的相应电压。 数据读取电路放大读取数据总线之间的电压差，以输出读取数据。 读取门的使用使读取数据总线能够与数据读取当前路径断开连接。 结果，快速地产生位线上的各个电压变化，从而可以提高数据读取速度。

公开(公告)号：US06445222B1

公开(公告)日：2002-09-03

申请号：US09708509

申请日：2000-11-09

申请人： Hideto Hidaka ,  Masakazu Hirose

发明人： Hideto Hidaka ,  Masakazu Hirose

IPC分类号： H03K300

CPC分类号： H03K19/00361

摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

摘要翻译： 当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。 当驱动晶体管导通时，输出节点以高速放电到地电位。 当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。 结果，输出节点的电位从高电平降低到中间电平，使得随后的输出信号的幅度减小。 提供了可以有效地防止产生振铃而不增加访问时间的输出电路。 提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。 高速提供稳定的输出信号。

公开(公告)号：US06414894B2

公开(公告)日：2002-07-02

申请号：US09778062

申请日：2001-02-07

申请人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

发明人： Tsukasa Ooishi ,  Takaharu Tsuji ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Hiroshi Kato

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

摘要翻译： 逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。 在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。 逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

公开(公告)号：US06404661B2

公开(公告)日：2002-06-11

申请号：US09464793

申请日：1999-12-16

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C506

CPC分类号： G11C5/14

摘要： A memory cell array includes a plurality of memory cells that are arranged in the row and column directions. Power supply lines and grounding lines are arranged on the memory cell array so as to extend in the column direction. The grounding lines are so arrayed that a plurality of power supply lines are interposed therebetween or, conversely, the power supply lines are so arranged that a plurality of grounding lines are interposed therebetween. By connecting together adjacent power supply lines (or grounding lines) of the same potential on a column decoder to form a single power line, the number of power supply lines extending in the column direction on the column decoder can be reduced, whereby an effective element forming region of the column decoder can be expanded.

摘要翻译： 存储单元阵列包括沿列和列方向布置的多个存储单元。 电源线和接地线布置在存储单元阵列上，以便在列方向上延伸。 接地线如此排列，使得多个电源线插入其间，或者相反地，电源线布置成使得多个接地线插入其间。 通过将列解码器上相同电位的相邻电源线（或接地线）连接在一起形成单个电源线，可以减少在列解码器上沿列方向延伸的供电线的数量，从而有效元件 可以扩展列解码器的形成区域。

公开(公告)号：US06313695B1

公开(公告)日：2001-11-06

申请号：US09301359

申请日：1999-04-29

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G05F110

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/747

摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

摘要翻译： 电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。 差分放大器控制连接到副电源线和次接地线的晶体管。 因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。 因此，可以在保持具有分层供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

公开(公告)号：US06292413B1

公开(公告)日：2001-09-18

申请号：US09288962

申请日：1999-04-09

申请人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroshi Kato ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C700

CPC分类号： G11C11/4074 ,  G11C8/12 ,  G11C29/846

摘要： In an SDRAM, a column decoder is split into four blocks, and a specific predecode signal is allocated to each block. A sub power supply line is provided in correspondence to each block, and a P-channel MOS transistor, having a relatively high threshold voltage, rendered conductive in response to the corresponding predecode signal is connected between the sub power supply line and a main power supply line. A power supply potential is supplied to only a selected block, for reducing a leakage current.

公开(公告)号：US06288949B1

公开(公告)日：2001-09-11

申请号：US09499368

申请日：2000-02-07

申请人： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

发明人： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

IPC分类号： G11C1140

CPC分类号： H01L27/10897 ,  G11C11/404 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

摘要： A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

公开(公告)号：US6104630A

公开(公告)日：2000-08-15

申请号：US197764

申请日：1998-11-23

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C5/14

摘要： A memory cell array includes a plurality of memory cells that are arranged in the row and column directions. Power supply lines and grounding lines are arranged on the memory cell array so as to extend in the column direction. The grounding lines are so arrayed that a plurality of power supply lines are interposed therebetween or, conversely, the power supply lines are so arranged that a plurality of grounding lines are interposed therebetween. By connecting together adjacent power supply lines (or grounding lines) of the same potential on a column decoder to form a single power line, the number of power supply lines extending in the column direction on the column decoder can be reduced, whereby an effective element forming region of the column decoder can be expanded.

摘要翻译： 存储单元阵列包括沿列和列方向布置的多个存储单元。 电源线和接地线布置在存储单元阵列上，以便在列方向上延伸。 接地线如此排列，使得多个电源线插入其间，或者相反地，电源线布置成使得多个接地线插入其间。 通过将列解码器上相同电位的相邻电源线（或接地线）连接在一起形成单个电源线，可以减少在列解码器上沿列方向延伸的供电线的数量，从而有效元件 可以扩展列解码器的形成区域。

公开(公告)号：US6060738A

公开(公告)日：2000-05-09

申请号：US546746

申请日：1995-10-23

申请人： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

发明人： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10873 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  Y10S148/15

摘要： In etching a polysilicon layer above a gate electrode layer, a portion of the gate electrode layer is left thereunder. The etching process of that polysilicon layer and that gate electrode layer is carried out in two steps of etching the polysilicon layer and an interlayer insulating layer, and etching the gate electrode layer and the gate oxide film. Therefore, the amount that is removed from an SOI layer can be suppressed in the manufacturing process thereof.

摘要翻译： 在蚀刻位于栅电极层上方的多晶硅层时，栅电极层的一部分留在其下。 该多晶硅层和该栅电极层的蚀刻工艺是在蚀刻多晶硅层和层间绝缘层的两个步骤中进行，蚀刻栅电极层和栅极氧化膜。 因此，能够抑制从SOI层除去的量。