公开(公告)号：US20210143324A1

公开(公告)日：2021-05-13

申请号：US16708389

申请日：2019-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Shih-Wei Su ,  Ting-An Chien

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01F10/32

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.

公开(公告)号：US10916694B2

公开(公告)日：2021-02-09

申请号：US16255754

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L41/47 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20200350199A1

公开(公告)日：2020-11-05

申请号：US16431684

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Hung-Chun Lee ,  Shu-Ming Yeh ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

公开(公告)号：US20200227354A1

公开(公告)日：2020-07-16

申请号：US16833713

申请日：2020-03-30

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  San-Fu Lin

IPC: H01L23/532 ,  H01L21/764 ,  H01L21/768 ,  H01L23/528

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.

公开(公告)号：US20200212290A1

公开(公告)日：2020-07-02

申请号：US16255754

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H01L21/762 ,  H01L43/02 ,  H01L21/768

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20200185264A1

公开(公告)日：2020-06-11

申请号：US16212362

申请日：2018-12-06

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US20200075395A1

公开(公告)日：2020-03-05

申请号：US16121605

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Lin ,  Chich-Neng Chang ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522

Abstract: An interconnection structure and method of forming the same are disclosed. A substrate is provided. A patterned layer is formed on the substrate and having at least a trench formed therein. A first dielectric layer is then formed on the patterned layer and sealing an air gap in the trench. Subsequently, a second dielectric layer is formed on the first dielectric layer and completely covering the patterned layer and the air gap. A curing process is then performed to the first dielectric layer and the second dielectric layer. A volume of the air gap is increased after the curing process.

公开(公告)号：US20190229053A1

公开(公告)日：2019-07-25

申请号：US15877340

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Jyuan Hung ,  Ai-Sen Liu ,  Bin-Siang Tsai ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L27/01

Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.

公开(公告)号：US10008409B2

公开(公告)日：2018-06-26

申请号：US15713724

申请日：2017-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chich-Neng Chang ,  Ya-Jyuan Hung ,  Bin-Siang Tsai

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/535 ,  H01L2221/1063

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a stop layer between the dielectric layer and the substrate, wherein the stop layer contacts the substrate directly and the dielectric layer covers the top surface of the stop layer; forming an opening in the dielectric layer, wherein the dielectric layer comprises a damaged layer adjacent to the opening; forming a dielectric protective layer in the opening; forming a metal layer in the opening; removing the damaged layer and the dielectric protective layer to form a void, wherein the void exposes a top surface of the substrate; and forming a cap layer on and covering the dielectric layer, the void, and the metal layer.

公开(公告)号：US09966425B1

公开(公告)日：2018-05-08

申请号：US15445953

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chin-Fu Lin ,  Bin-Siang Tsai ,  Xu Yang Shen ,  Seng Wah Liau ,  Yen-Chen Chen ,  Ko-Wei Lin ,  Chun-Ling Lin ,  Kuo-Chih Lai ,  Ai-Sen Liu ,  Chun-Yuan Wu ,  Yang-Ju Lu

IPC: H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/60

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.