公开(公告)号：US09274413B2

公开(公告)日：2016-03-01

申请号：US14023472

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/311 ,  G03F1/38 ,  H01L21/308

CPC classification number: G03F1/38 ,  G03F1/70 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845

Abstract: A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate.

Abstract translation: 用于形成布局图案的方法包括以下处理。 首先，在第一掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模，第二掩模， 和第三个掩模。 然后，转移第一布局图案以形成第一图案层。 之后，在第一图案化层的侧壁上形成具有第一临界尺寸的间隔物，从而构成环形图案。 然后，转移第三布局图案以形成具有第二临界尺寸的第二图案层，其中第二临界尺寸大于第一临界尺寸。 最后，将环状图案，焊盘图案和虚拟焊盘图案转印到基板上的目标层中。

公开(公告)号：US20160005658A1

公开(公告)日：2016-01-07

申请号：US14462574

申请日：2014-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract translation: 金属栅极结构包括具有致密区域和iso区域的基板。 第一金属栅极结构设置在致密区域内，第二金属栅极结构设置在iso区域内。 第一金属栅极结构包括设置在致密区域内的第一沟槽和设置在第一沟槽内的第一金属层。 第二金属栅极结构包括设置在iso区内的第二沟槽和设置在第二沟槽内的第二金属层。 第二金属层的高度大于第一金属层的高度。

公开(公告)号：US09070635B2

公开(公告)日：2015-06-30

申请号：US13963688

申请日：2013-08-09

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Yu-Cheng Tung

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/76224 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.

Abstract translation: 一种移除方法，包括以下步骤。 将衬底转移到蚀刻机中，其中衬底具有形成在其上的材料层。 执行循环过程。 循环过程包括执行蚀刻工艺以去除材料层的一部分，以及执行退火处理以除去由蚀刻工艺产生的副产物。 循环过程至少重复一次。 将基板转移出蚀刻机。 在本发明的除去方法中，进行多次循环处理以有效地去除材料层的不希望的厚度并降低负载效果。

公开(公告)号：US20150044879A1

公开(公告)日：2015-02-12

申请号：US13963688

申请日：2013-08-09

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Yu-Cheng Tung

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/76224 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.

Abstract translation: 一种移除方法，包括以下步骤。 将衬底转移到蚀刻机中，其中衬底具有形成在其上的材料层。 执行循环过程。 循环过程包括执行蚀刻工艺以去除材料层的一部分，以及执行退火工艺以除去由蚀刻工艺产生的副产物。 循环过程至少重复一次。 将基板转移出蚀刻机。 在本发明的除去方法中，进行多次循环处理以有效地去除材料层的不希望的厚度并降低负载效果。

公开(公告)号：US11205710B2

公开(公告)日：2021-12-21

申请号：US16357333

申请日：2019-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US20210242018A1

公开(公告)日：2021-08-05

申请号：US17218112

申请日：2021-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

公开(公告)号：US10825817B2

公开(公告)日：2020-11-03

申请号：US15857642

申请日：2017-12-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L27/02

Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.

公开(公告)号：US10818660B2

公开(公告)日：2020-10-27

申请号：US16407188

申请日：2019-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US10790202B2

公开(公告)日：2020-09-29

申请号：US16368795

申请日：2019-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  H01L23/544 ,  G03F7/20

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10571796B2

公开(公告)日：2020-02-25

申请号：US15585000

申请日：2017-05-02

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/24 ,  G03F1/52 ,  G03F1/54 ,  G03F1/80

Abstract: An extreme ultraviolet (EUV) photomask includes a mask substrate, a reflection layer and a light-absorbing pattern layer. The reflection layer is disposed on the mask substrate, wherein the reflection layer has a concave pattern. The light-absorbing pattern layer is in the reflection layer, to fill the concave pattern. The light-absorbing pattern layer is exposed.