公开(公告)号：US20130223138A1

公开(公告)日：2013-08-29

申请号：US13836690

申请日：2013-03-15

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract translation: 安全存储器包括具有编程的启动状态的双稳态存储单元，以及用于响应于翻转信号翻转单元的状态的装置。 存储器可以包括用于以例如小于发射显微镜的获取时间的周期产生翻转信号的时钟。

公开(公告)号：US20130214326A1

公开(公告)日：2013-08-22

申请号：US13768730

申请日：2013-02-15

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Galy ,  Nicolas Guitard ,  Thomas Benoist

IPC: H01L29/74

CPC classification number: H01L29/7424 ,  H01L27/0262 ,  H01L29/87

Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

Abstract translation: 一种器件包括在绝缘体上的硅层内的包括具有第一类型导电性的中心区域的中心半导体区域，具有与第一类型导电性相反的第二类型导电率的第二类型的中间区域分别设置在 并且与中心区域接触以形成两个PN结，两个半导体端部区域分别设置在中心区域的任一侧上，每个端部区域包括与相邻中间区域接触的相反导电类型的两个端部区域， 每个端部区域的两个端部区域相互电连接以形成装置的两个端子。

公开(公告)号：US08495734B2

公开(公告)日：2013-07-23

申请号：US12485334

申请日：2009-06-16

Applicant: Frederic Bancel ,  Nicolas Berard ,  David Hely

Inventor： Frederic Bancel ,  Nicolas Berard ,  David Hely

IPC: G06F11/00

CPC classification number: G06F21/554 ,  G06F21/77

Abstract: The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits.

Abstract translation: 本公开涉及一种用于由处理器执行在程序存储器中读取的程序的方法，包括以下步骤：检测程序存储器读地址跳转; 在用于跳转程序存储器读地址的跳转地址指令之前提供用于存储跳转地址指令的存在的指令; 并且如果已经检测到地址跳转并且还没有存储跳转地址指令的存在，则激活错误信号。 本公开还涉及固定集成电路。

公开(公告)号：US08488843B2

公开(公告)日：2013-07-16

申请号：US13560258

申请日：2012-07-27

Applicant: Lionel Martin ,  Salah Bourennane ,  Simon Conseil

Inventor： Lionel Martin ,  Salah Bourennane ,  Simon Conseil

IPC: G06K9/00

CPC classification number: G06K9/00355 ,  E05F15/00 ,  E05Y2400/852 ,  E05Y2400/86 ,  G06K9/00375 ,  G06K9/00389

Abstract: A method for following hand movements in an image flow, includes receiving an image flow in real time, locating in each image in the received image flow a hand contour delimiting an image zone of the hand, extracting the postural characteristics from the image zone of the hand located in each image, and determining the hand movements in the image flow from the postural characteristics extracted from each image. The extraction of the postural characteristics of the hand in each image includes locating in the image zone of the hand the center of the palm of the hand by searching for a pixel of the image zone of the hand the furthest from the hand contour.

Abstract translation: 一种用于在图像流中跟随手移动的方法，包括实时地接收图像流，在接收到的图像流中定位每个图像中定义手图像区域的手轮廓，从图像区域中提取姿势特征 并且从从每个图像提取的姿势特征中确定图像流中的手的移动。 提取每个图像中的手的姿势特征包括通过搜索最远离手轮廓的手的图像区域的像素来定位在手掌的中心的手的图像区域中。

公开(公告)号：US08483630B2

公开(公告)日：2013-07-09

申请号：US13122889

申请日：2009-10-06

Applicant: Andrea Cathelin ,  Stéphane Thuries ,  Sylvain Godet ,  Eric Tournier ,  Jacques Graffeuil

Inventor： Andrea Cathelin ,  Stéphane Thuries ,  Sylvain Godet ,  Eric Tournier ,  Jacques Graffeuil

IPC: H03C1/52

CPC classification number: H04B1/7174

Abstract: System for generating a pulsed signal of the ultra wideband type, comprising a device for direct digital frequency synthesis (DDS) comprising a phase accumulator (ACCP) able to deliver at a first frequency (Fclk) phases coded on i bits and spaced apart by a phase increment (Δp) differing by a power of two and situated in the vicinity of 2i-1, processing means (MT) able to receive said phases and arranged so as to deliver an amplitude-modulated output signal (SG) whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude (ZA, ZB), each amplitude-modulated signal part situated in one of said regions forming a pulse of the ultra wideband type (IMP) whose central frequency is equal to said first frequency and whose width depends on the value of the phase increment, and control means (MC) able to regulate the operation of the digital synthesis device so as to selectively deliver one or more pulses of the ultra wideband type.

Abstract translation: 用于产生超宽带类型的脉冲信号的系统，包括用于直接数字频率合成（DDS）的装置，其包括相位累加器（ACCP），所述相位累加器能够以在i比特上编码的第一频率（Fclk）相位传送，并由 相位增量（Deltap），其功率为2并位于2i-1附近，处理装置（MT）能够接收所述相位并被布置成传送调幅输出信号（SG），其幅度为 分别由零幅度区域（ZA，ZB）限定的区域的连续区域，位于所述区域之一中的每个幅度调制信号部分形成中心频率等于所述第一频率的超宽带类型（IMP）的脉冲， 宽度取决于相位增量的值，以及能够调节数字合成装置的操作以便选择性地传送超宽带类型的一个或多个脉冲的控制装置（MC）。

公开(公告)号：US08468438B2

公开(公告)日：2013-06-18

申请号：US12880844

申请日：2010-09-13

Applicant: Vincent Heinrich ,  Julien Begey

Inventor： Vincent Heinrich ,  Julien Begey

IPC: G06F11/00 ,  H03M13/00

CPC classification number: H03M13/13 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1171 ,  H03M13/6502 ,  H03M13/6505

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract translation: 在用所述LDPC码编码的块的解码期间，对非二进制LDPC码的校验节点进行基本更新的方法，包括接收第一输入消息（U）和第二输入消息（V），每个包括具有符号 和相关联的度量，通过基于两个输入消息（U，V）的双重组合的计算nm2组合双精度的矩阵来传送具有nm输出双精度的输出消息（S），并且减少 组合双重，以获得具有nm最大或最小度量的输出消息（S）的nm输出双倍。 该方法还包括在每个输入消息（U，V）中标记冗余符号并且以参考值固定相同的值，由包括标记的冗余符号的至少一个双工的组合产生的每个组合双精度的度量值。

公开(公告)号：US08458556B2

公开(公告)日：2013-06-04

申请号：US12900584

申请日：2010-10-08

Applicant: Shiva K. Planjery ,  Shashi Kiran Chilappagari ,  Bane Vasic ,  David Declercq

Inventor： Shiva K. Planjery ,  Shashi Kiran Chilappagari ,  Bane Vasic ,  David Declercq

IPC: H03M13/00

CPC classification number: H03M13/1171 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/3707 ,  H03M13/6577 ,  H04L1/005 ,  H04L1/0057

Abstract: In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.

Abstract translation: 在本发明中，提出了一种新型的用于低密度奇偶校验（LDPC）码的有限精度多级解码器。 与标准置信传播（BP）解码器相比，这些解码器的复杂度要低得多。 由这些解码器使用的消息基于允许在硬件中表示的比特数被量化到某个等级。 特定定义为本发明一部分的消息更新功能用于确定可变节点处的传出消息，并且在校验节点处使用简单最小操作以及模2符号和。 提供了一种通用的方法来获得多级解码器，该解码器基于减少陷阱集合造成的故障并提高代码的有保障的纠错能力。 因此，这些解码器改进了有限长度图上的迭代解码过程，并且具有在误差区域中优于标准浮点BP解码器的潜力。 还提出了用于列重三个LDPC码的3位解码器的描述和装置。

公开(公告)号：US08436652B2

公开(公告)日：2013-05-07

申请号：US13152008

申请日：2011-06-02

Applicant: Sylvain Engels

Inventor： Sylvain Engels

IPC: H03K19/173

CPC classification number: H03K3/037

Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.

Abstract translation: 顺序电子电路（10）在包括第一（1）和第二（2）D型触发器的时钟信号（CK）的上升沿和下降沿上反应，主复用器（3） 输入到触发器（1和2），电路（10）包括接收时钟信号（CK）的第一输入端和接收控制信号（TE）的第二输入端，以便根据 正常操作模式和测试操作模式，使得可以检查顺序电子电路（10）的正常操作。 在正常操作模式下使用的时钟信号（CK）用于在测试操作模式期间门电路（10）。

公开(公告)号：US08412996B2

公开(公告)日：2013-04-02

申请号：US12020812

申请日：2008-01-28

Applicant: Frederic Bancel ,  Nicolas Berard ,  Philippe Roquelaure

Inventor： Frederic Bancel ,  Nicolas Berard ,  Philippe Roquelaure

IPC: G06F11/00 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  G11B27/00 ,  G01R31/28 ,  H03M13/00 ,  H04L7/00

CPC classification number: G06K19/07363

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract translation: 装置和方法检测由逻辑信号的至少两个变化边缘的接近程度超过接近阈值表示的逻辑信号的加速度。 提供第一控制位和第二控制位。 在逻辑信号的每个边缘处，第一控制位的值在第一延迟之后被反转，并且第二控制位的值在第二延迟之后被反转。 当两个控制位同时具有各自的初始值或其各自的反相初始值时，检测到加速度。 特别地，但不限于对安全集成电路中的错误注入的检测的应用。

公开(公告)号：US20130075870A1

公开(公告)日：2013-03-28

申请号：US13622573

申请日：2012-09-19

Applicant: STMicoelectronics (Crolles 2) SAS ,  STMicroelectronics SA,

Inventor： Didier Dutartre ,  Michel Marty ,  Sebastien Jouan

IPC: H01L21/3105 ,  H01L23/58

CPC classification number: H01L21/76898 ,  H01L21/76251

Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.

Abstract translation: 一种器件和相应的制造方法包括在下部区域和上部区域之间具有中间层的垂直堆叠。 中间层由保护层延伸。 垂直堆叠具有自由侧面，下部区域，上部区域和保护层暴露在该侧面上。