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    DATA DISTRIBUTION DEVICE AND DATA DISTRIBUTION METHOD
    145.
    发明申请
    DATA DISTRIBUTION DEVICE AND DATA DISTRIBUTION METHOD 审中-公开
    数据分配设备和数据分配方法

    公开(公告)号：US20090021519A1

    公开(公告)日：2009-01-22

    申请号：US12140339

    申请日：2008-06-17

    申请人： Atsushi Yusa

    发明人： Atsushi Yusa

    IPC分类号： G06F13/00

    CPC分类号： G09G3/3688 ,  G09G5/395 ,  G09G5/397 ,  G09G2310/0221 ,  G09G2340/14 ,  G09G2360/126

    摘要： A data distribution device includes a pair of first storage units, a second storage unit which includes a dual-port memory, a write unit which repeatedly writes drive data into one of the pair of first storage units and thereafter writes the remaining drive data and a read output unit which outputs the respective concurrently read drive data to the k corresponding drive circuits concurrently, where read addresses read from the dual-port memory are not overtaken by write addresses written to the dual-port memory during the period in which reading and writing of the drive data are being simultaneously performed with respect to the dual-port memory of the second storage unit.

    摘要翻译： 数据分配装置包括一对第一存储单元，包括双端口存储器的第二存储单元，将驱动数据重复地写入一对第一存储单元中的一个的写单元，然后写入剩余的驱动数据和 读取输出单元，其将相应的同时读取的驱动数据同时输出到k个对应的驱动电路，其中从双端口存储器读取的读取地址在写入到双端口存储器的写入地址期间不被读取和写入 相对于第二存储单元的双端口存储器正在同时执行驱动数据。

    Availability of space in a RISC microprocessor architecture
    148.
    发明申请
    Availability of space in a RISC microprocessor architecture 审中-公开
    RISC微处理器架构中空间的可用性

    公开(公告)号：US20070271441A1

    公开(公告)日：2007-11-22

    申请号：US11881283

    申请日：2007-07-26

    申请人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    发明人： George Shaw ,  Martin McClurg ,  Bradley Jensen ,  Russell Fish ,  Charles Moore

    IPC分类号： G06F15/00

    CPC分类号： G06F12/0875 ,  G06F9/30014 ,  G06F9/3005 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/126

    摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

    摘要翻译： 微处理器以100 MHz内部时钟频率执行100个本机MIPS峰值性能。 中央处理单元（CPU）指令集是硬连线的，允许大多数指令在一个周期内执行。 “流通”设计允许下一条指令在先前指令完成之前启动，从而提高性能。 微处理单元（MPU）包含52个通用寄存器，包括16个全局数据寄存器，一个索引寄存器，一个计数寄存器，一个16深可寻址寄存器/返回堆栈以及一个18深操作数堆栈。 两个堆栈都包含顶部元素中的索引寄存器，缓存在芯片上，并在需要时自动溢出并从外部存储器中重新填充。 堆栈最小化数据移动，并在过程调用，参数传递和变量赋值期间最小化存储器访问。 此外，MPU还包含一个模式/状态寄存器和41个用于I / O，控制，配置和状态的本地寻址寄存器。 CPU包含高性能零操作数双堆栈架构MPU和执行指令传输数据，计数事件，测量时间和执行其他与时序相关的功能的输入输出处理器（IOP）。 零操作数堆栈架构消除了操作数位。 堆栈还可以在过程内和跨过程中最小化寄存器保存和加载，从而允许较短的指令序列和更快的运行代码。 指令简单易于解码和执行，允许MPU和IOP在单个时钟周期内发出和完成指令，每个时钟周期为100个本机MIPS峰值执行。 每次执行指令提取或预取时，CPU使用8位操作码，最多可从内存中获取四条指令。 这些指令可以重复，而不会从内存重新读取。 当直接连接到DRAM而没有高速缓存时，这将保持高性能。

    Method and device for accessing frame memory within display panel driver
    149.
    发明授权
    Method and device for accessing frame memory within display panel driver 失效
    用于在显示面板驱动程序中访问帧存储器的方法和设备

    公开(公告)号：US07180521B2

    公开(公告)日：2007-02-20

    申请号：US10713005

    申请日：2003-11-17

    申请人： Toshiaki Inoue ,  Katsuyuki Hashimoto

    发明人： Toshiaki Inoue ,  Katsuyuki Hashimoto

    IPC分类号： G09G5/39 ,  G09G5/36 ,  G06F13/28

    CPC分类号： G09G3/2022 ,  G06F3/038 ,  G09G3/288 ,  G09G5/393 ,  G09G2360/126

    摘要： A method for accessing a frame memory integrated within a display panel driver driving a display panel is composed of serially performing write operations for writing sub-field data of a pixel line within the display panel for a plurality of sub-fields into the frame memory, and serially performing read operations for reading sub-field data of a plurality of pixel lines for a sub-field from the frame memory. At least two of the write operations are allowed to be performed between adjacent two of the read operations.

    摘要翻译： 用于访问集成在驱动显示面板的显示面板驱动器内的帧存储器的方法由串行执行写入操作组成，用于将用于多个子场的显示面板内的像素线的子场数据写入帧存储器， 并且从帧存储器中串行地执行读取用于子场的多个像素线的子场数据的读取操作。 允许在相邻的两个读取操作之间执行至少两个写入操作。

    Device and method for displaying video
    150.
    发明授权
    Device and method for displaying video 失效
    用于显示视频的设备和方法

    公开(公告)号：US06928118B1

    公开(公告)日：2005-08-09

    申请号：US09647538

    申请日：2000-01-28

    申请人： Takashi Otome

    发明人： Takashi Otome

    IPC分类号： G09G5/00 ,  H04N7/18

    CPC分类号： H04N5/44504 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G2310/0224 ,  G09G2340/125 ,  G09G2360/126

    摘要： A video display apparatus and method capable of providing, even if an on-screen display device that operates only on a clock lower in speed than a dot clock synchronized with a video signal is used, high-definition on-screen display based on the dot clock. Based on a signal outputted from a control signal generator 1, a line memory 3 writes the on-screen signal outputted from an OSD generator 2 on a clock (CK2) lower in speed than the dot clock of the video signal, and reads the same on a clock (CK1) synchronized with the dot clock of the video signal. A switching part 4 inserts the on-screen signal synchronized with the dot clock of the video signal outputted from the line memory 3 into a predetermined period of the video signal by selectively switching outputs.

    摘要翻译： 即使使用仅在比与视频信号同步的点时钟低的时钟上工作的屏幕显示装置的视频显示装置和方法也可以提供基于点的高清晰度屏幕显示 时钟。 基于从控制信号发生器1输出的信号，行存储器3将从OSD生成器2输出的屏上信号写入比视频信号的点时钟低的时钟（CK 2），并读取 在与视频信号的点时钟同步的时钟（CK 1）上相同。 切换部分4通过选择性地切换输出，将与行存储器3输出的视频信号的点时钟同步的屏幕信号插入视频信号的预定周期。