公开(公告)号：US07982510B2

公开(公告)日：2011-07-19

申请号：US12573253

申请日：2009-10-05

Applicant: Arnaud Casagrande

Inventor： Arnaud Casagrande

IPC: H03L7/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991

Abstract: The frequency synthesizer for implementing a self-calibration method includes (i) a first phase lock loop comprising: a reference oscillator, a phase comparator, a first charge pump, a first loop filter, a voltage controlled oscillator, and a multimode divider counter controlled by a modulator and connected to the phase comparator; (ii) a high frequency access comprising a digital-analogue converter connected to an input of the voltage-controlled oscillator; (iii) a second charge pump connected to the phase comparator; and (iv) a second loop filter in the high frequency access. The second charge pump forms, when switched on, a second phase lock loop with the second loop filter. To calibrate gains of the converter, a voltage comparator compares an output voltage of the converter with a voltage stored in the second loop filter, after disconnecting the second charge pump from the second phase lock loop, previously locked onto a determined output frequency.

Abstract translation: 用于实现自校准方法的频率合成器包括：（i）第一锁相环，包括：参考振荡器，相位比较器，第一电荷泵，第一环路滤波器，压控振荡器和多模除法器控制 通过调制器连接到相位比较器; （ii）包括连接到所述压控振荡器的输入的数模转换器的高频接入; （iii）连接到相位比较器的第二电荷泵; 和（iv）高频接入中的第二环路滤波器。 第二个电荷泵在接通时形成具有第二环路滤波器的第二个锁相环。 为了校准转换器的增益，电压比较器将先前锁定到确定的输出频率上的第二电荷泵与第二锁相环断开之后，将转换器的输出电压与存储在第二环路滤波器中的电压进行比较。

公开(公告)号：US07979038B2

公开(公告)日：2011-07-12

申请号：US12160874

申请日：2007-01-16

Applicant: Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

Inventor： Yosuke Mitani ,  Shunsuke Hirano ,  Kaoru Ishida

IPC: H04B1/04

CPC classification number: H03L7/1976 ,  H03C3/0908 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

Abstract: Provided are a PLL modulation circuit, a radio transmission device, and a radio communication device capable of maintaining a modulation accuracy for modulation of a wide band. The PLL modulation circuit (100) includes: a PLL unit (110), first modulation signal input means for inputting a first modulation signal to a divider (112) or a phase comparator (113) of the PLL unit (110); second modulation signal input means for DA converting the digital modulation signal in a DA converter (116) to generate an analog second modulation signal and inputting it to a voltage control oscillator (111) of the PLL unit (110); a second divider for dividing the output signal of the voltage control oscillator (111); and control means for generating a center frequency control signal, a gain control signal, and a second division ration control signal according to the channel selection signal and the control voltage inputted to the voltage control oscillator (111) and supplying them to the divider (112), the DA converter (116), and the second divider (114), respectively.

Abstract translation: 提供了能够维持宽带调制的调制精度的PLL调制电路，无线发送装置以及无线通信装置。 PLL调制电路（100）包括：PLL单元（110），用于将第一调制信号输入到PLL单元（110）的分频器（112）或相位比较器（113）的第一调制信号输入装置; 第二调制信号输入装置，用于在DA转换器（116）中转换数字调制信号，以产生模拟第二调制信号并将其输入到PLL单元（110）的电压控制振荡器（111）; 用于分压电压控制振荡器（111）的输出信号的第二分频器; 以及控制装置，用于根据输入到电压控制振荡器（111）的通道选择信号和控制电压产生中心频率控制信号，增益控制信号和第二分频控制信号，并将其提供给分频器（112） ），DA转换器（116）和第二分频器（114）。

公开(公告)号：US07940142B2

公开(公告)日：2011-05-10

申请号：US12506997

申请日：2009-07-21

Applicant: Henrik T. Jensen ,  Brima B. Ibrahim

Inventor： Henrik T. Jensen ,  Brima B. Ibrahim

IPC: H03C3/20 ,  H03C3/06

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/093

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract translation: 极性发射机包括用于产生宽带宽的RF信号的两点调制锁相环（PLL）。 PLL包括用于接收可变包络调制信号的相位信号并沿着第一信号路径提供相位信号以产生第一频率调制信号的第一输入端和用于接收相位信号并提供相位信号的第二输入端 用于产生第二频率调制信号的第二信号路径。 PLL还包括具有两个调制点的压控振荡器（VCO），一个用于接收第一频率调制信号，另一个用于接收第二频率调制信号。 VCO由第一频率调制信号和第二频率调制信号的集合控制，以将来自IF的相位信号上变频到RF以产生具有宽带宽的RF信号。

公开(公告)号：US20110032040A1

公开(公告)日：2011-02-10

申请号：US12535753

申请日：2009-08-05

Applicant: Kenneth Beghini

Inventor： Kenneth Beghini

IPC: H03L7/00

CPC classification number: H04B1/0075 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/183 ,  H03L7/23 ,  H04L27/12 ,  H04L27/206 ,  H04L27/362

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract translation: 通信设备（100）包括具有多个分频比的分频器电路（106）。 该装置还包括耦合到分频器电路的至少一个信号输入的至少一个锁相环（PLL）电路（101,102,103,104,110,112）。 PLL电路包括包括具有不同频率调谐范围的多个压控振荡器（VCO）的本地振荡器（LO）电路（104）。 该装置还包括耦合到至少分频器电路和PLL电路的至少一个控制输入（105），用于指定多个VCO中的一个并且分频器电路的多个分频比之一。

公开(公告)号：US07800452B2

公开(公告)日：2010-09-21

申请号：US11976408

申请日：2007-10-24

Applicant: Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

Inventor： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC: H03L7/00

CPC classification number: H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Abstract translation: 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US07755444B2

公开(公告)日：2010-07-13

申请号：US12090727

申请日：2006-10-18

Applicant: Paul Mattheijssen ,  Dominicus Martinus Wilhelmus Leenaerts

Inventor： Paul Mattheijssen ,  Dominicus Martinus Wilhelmus Leenaerts

IPC: H03C3/02 ,  H03C3/40

CPC classification number: H03C3/0941 ,  H03C3/095 ,  H03C3/0975 ,  H03C5/00 ,  H04L27/361

Abstract: The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (40). As an example, the processing may be based on a differentiate-and-multiply algorithm in the analog domain. Thereby, phase and envelope signals are generated in the analog domain and bandwidth enlargement due to the processing of the polar signals and corresponding aliasing can be prevented to obtain a highly accurate polar-modulated output signal.

Abstract translation: 本发明涉及一种极坐标调制装置和方法，其中在模拟域中处理同相和正交相位信号以产生对应于所述极坐标调制信号的相位分量的微分的模拟信号。 然后将模拟信号输入到受控振荡器（40）的控制输入端。 作为示例，处理可以基于模拟域中的差分和乘法算法。 因此，在模拟域中产生相位和包络信号，并且由于极坐标信号的处理而导致带宽放大，可以防止相应的混叠，从而获得高精度的极调制输出信号。

公开(公告)号：US07750750B2

公开(公告)日：2010-07-06

申请号：US12115068

申请日：2008-05-05

Applicant: Sofoklis Plevridis ,  Theodoros Georgantas ,  Konstantinos D. Vavelidis

Inventor： Sofoklis Plevridis ,  Theodoros Georgantas ,  Konstantinos D. Vavelidis

IPC: H03C3/00

CPC classification number: H03C5/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract translation: 用于发射机的增强极化调制器。 在锁相环（PLL）中，使用两点调制拓扑，其中相位信息通过限制器（例如，+ 90°或+ re / 2），其中相位信息动态范围除以因子 例如，通过2）和最大频率偏差也除以因子（例如，2）。 然后，实现双平衡上变频混频器/调制器来执行增益调整（例如，幅度和/或幅度调整）以及0°和+ 180°或0和+ re的相位变化（例如，负增益值可以是 就业）。 这种架构中的相位调整被分离并提供给发射机模块内的PLL和这种极性调制器的混频器/调制器，例如可以在通信设备（例如，其可以是无线通信设备）内实现。 这种包括具有双平衡上变频混频器/调制器的PLL的架构抑制了偶次谐波。

公开(公告)号：US20100141313A1

公开(公告)日：2010-06-10

申请号：US12330885

申请日：2008-12-09

Applicant: Jifeng Geng ,  Gary John Ballantyne ,  Daniel F. Filipovic

Inventor： Jifeng Geng ,  Gary John Ballantyne ,  Daniel F. Filipovic

IPC: H03L7/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

Abstract: A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.

Abstract translation: 描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。 在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。 在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。 内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。

公开(公告)号：US07706495B2

公开(公告)日：2010-04-27

申请号：US11078701

申请日：2005-03-14

Applicant: Shunsuke Hirano ,  Mamoru Arayashiki

Inventor： Shunsuke Hirano ,  Mamoru Arayashiki

IPC: H03D3/24

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

Abstract: A two-point frequency modulation apparatus is proposed whereby the spectrum of transmission waves is kept within the spectrum mask. Voltage is supplied to the control voltage terminal of VCO 1 in accordance with modulation data via noise shaper 101 that has operating characteristics of attenuating more noise at higher frequencies. As a result, by virtue of the working of noise shaper 101, the signal level outputted from the PLL circuit combining the modulation signal and the quantization noise decreases in proportion to the distance form the central frequency, so that two-point frequency modulation apparatus 100 is made possible whereby the spectrum of an RF modulation signal is kept within the spectrum mask.

Abstract translation: 提出了两点式调制装置，其中发射波的频谱保持在频谱掩模内。 电压根据调制数据通过噪声整形器101提供给VCO1的控制电压端，噪声整形器101具有在较高频率下衰减更多噪声的操作特性。 结果，通过噪声整形器101的工作，组合调制信号和量化噪声的PLL电路输出的信号电平与中心频率的距离成比例地减小，使得两点式调频装置100 使得RF调制信号的频谱保持在频谱掩模内。

公开(公告)号：US20100066459A1

公开(公告)日：2010-03-18

申请号：US12585319

申请日：2009-09-11

Applicant: Hyung-Ki Ahn

Inventor： Hyung-Ki Ahn

IPC: H03C3/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991

Abstract: A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.

Abstract translation: 提供了两点相位调制器和校准其转换增益的方法。 两点相位调制器通过在操作开始时在锁相环（PLL）电路中充电和抽取电荷来锁定输出频率信号，打开PLL电路的一个环路一段时间，并施加步进信号 ，从而校准控制输出频率信号的调制信号的转换增益。 因此，可以通过一次的校准操作来精确地校准转换增益。