公开(公告)号：US20070077703A1

公开(公告)日：2007-04-05

申请号：US11560902

申请日：2006-11-17

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L21/8242

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42324

Abstract: Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the peripheral circuit region. A cell gate pattern that includes a plurality of conductive layers crosses over the cell active region, and a peripheral gate pattern that includes a plurality of conductive layers crosses over the peripheral active region. A lowermost layer of the peripheral gate pattern has first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer. Further, the lowest layer of the cell gate pattern and the lowest layer of the peripheral gate pattern comprise different conductive layers.

Abstract translation: 半导体器件设置在具有单元阵列区域和外围电路区域的基板上。 第一器件隔离层限定电池阵列区域中的电池有源区，并且具有第一和第二侧壁的第二器件隔离层限定外围电路区域中的外围有源区。 包括多个导电层的单元栅极图案与单元有源区交叉，并且包括多个导电层的外围栅极图案跨过周边有源区。 外围栅极图案的最下层具有与第二器件隔离层的第一和第二侧壁的相应的第一和第二侧壁或第二器件隔离层的第一和第二侧壁的垂直延伸部对准的第一和第二侧壁。 此外，单元栅极图案的最下层和外围栅极图案的最下层包括不同的导电层。

公开(公告)号：US20070073231A1

公开(公告)日：2007-03-29

申请号：US11434878

申请日：2006-05-17

Applicant: Chang-Hyun Lee ,  Tao-Seo Kim ,  Hyun-Ook Kim ,  Jae-Hyun Park

Inventor： Chang-Hyun Lee ,  Tao-Seo Kim ,  Hyun-Ook Kim ,  Jae-Hyun Park

IPC: A61M37/00

CPC classification number: A61M35/003 ,  A61F9/0008 ,  A61M2210/0612 ,  B65D47/18

Abstract: A medicinal solution dripping nozzle is used to drop a predetermined dosage of medicinal solution in a form of droplet. The medicinal solution dripping nozzle includes a nozzle portion for defining a flow path, and a guide member fixedly positioned midway the nozzle portion. The guide member includes a base portion and a protrusion portion projected on the base portion wherein the base portion has at least two holes communicating with a medicinal solution chamber. Therefore, the medicinal solution is discharged through the holes from the medicinal solution chamber and guided to a tip end of the guide member while forming the droplet.

Abstract translation: 使用药液滴注嘴以液滴形式滴下预定剂量的药液。 药液滴注嘴包括用于限定流路的喷嘴部分和固定地位于喷嘴部分的中间的引导部件。 引导构件包括基部和突出部，突出在基部上，其中基部具有与药液室连通的至少两个孔。 因此，药液通过孔从药液室排出，并在形成液滴的同时被引导至引导构件的前端。

公开(公告)号：US07170795B2

公开(公告)日：2007-01-30

申请号：US11128038

申请日：2005-05-12

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

Abstract translation: 电可擦除电荷陷阱非易失性存储单元具有初始阈值电压，高于初始阈值电压的编程电压和低于编程阈值电压但高于初始阈值电压的擦除阈值电压。 可以通过施加足以将晶体管的阈值电压从编程阈值电压降低到低于编程阈值电压的擦除阈值电压的时间间隔施加擦除电压来擦除编程的电可擦除电荷陷阱非易失性存储器单元， 但高于初始阈值电压。 可以通过使用从初始时间间隔增加或减少的时间间隔重复执行耐久性测试来获得时间间隔，以获得满足耐久性规范的时间间隔，或允许成功执行读取。

公开(公告)号：US07157548B2

公开(公告)日：2007-01-02

申请号：US10486883

申请日：2002-08-21

Applicant: Young-Moo Lee ,  Ho-Burn Park ,  Chang-Hyun Lee

Inventor： Young-Moo Lee ,  Ho-Burn Park ,  Chang-Hyun Lee

IPC: C08G73/10

CPC classification number: C08G73/10

Abstract: The present invention relates to a new sulfonated polyimides, more specifically to new methods for preparing the polyimides, and cation exchange membranes containing the polyimides. The sulfonated polyimides of the presented invention have excellent proton conductivity and low preparation cost. In particular, the sulfonated polyimides can be used as polymer electrolyte membrane in hydrogen or direct methanol fuel cell for electric vehicles and portable power sources operated with electric energy

Abstract translation: 本发明涉及新的磺化聚酰亚胺，更具体地涉及制备聚酰亚胺的新方法和含有聚酰亚胺的阳离子交换膜。 本发明的磺化聚酰亚胺具有优异的质子传导性和低的制备成本。 特别地，磺化聚酰亚胺可以用作氢气中的聚合物电解质膜或用于电动车辆的直接甲醇燃料电池和用电能操作的便携式电源

公开(公告)号：US20060289944A1

公开(公告)日：2006-12-28

申请号：US11474699

申请日：2006-06-23

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

公开(公告)号：US20060250850A1

公开(公告)日：2006-11-09

申请号：US11381579

申请日：2006-05-04

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

公开(公告)号：US20060240623A1

公开(公告)日：2006-10-26

申请号：US11471798

申请日：2006-06-21

Applicant: Chang-Hyun Lee ,  Dong-Gun Park

Inventor： Chang-Hyun Lee ,  Dong-Gun Park

IPC: H01L21/336

CPC classification number: H01L21/265 ,  B82Y10/00 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract translation: 在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。 电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。 在电荷存储图案上提供栅极图案。 在电荷存储图案和栅极图案之间设置隔离绝缘层。 电荷存储图案的侧壁包括第一氮掺杂层。 本文还提供了制造非易失性存储器件的相关方法。

公开(公告)号：US07087489B2

公开(公告)日：2006-08-08

申请号：US10429153

申请日：2003-05-01

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546

Abstract: A method of forming a trap type nonvolatile memory device is disclosed. The method includes forming a cell gate insulating layer on a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region and a cell array region. A sacrificial pattern is formed on the cell gate insulating layer to cover the cell array region. The cell gate insulating layer in the peripheral circuit region is then etched using the sacrificial pattern as an etch mask to expose the semiconductor substrate in the peripheral circuit region. The cell gate insulating layer includes a lower insulating layer, a charge storage layer, and an upper insulating layer. Also, the upper insulating layer and the sacrificial pattern are made of material layers having an etch selectivity with respect to each other. The upper insulating layer is made of a metal oxide layer having an etch selectivity with respect to the sacrificial pattern.

公开(公告)号：US07084030B2

公开(公告)日：2006-08-01

申请号：US10632496

申请日：2003-07-31

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Wang-Chul Shin

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/792

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract translation: 非易失性存储器件包括具有电荷存储层的存储器栅极图案的单元区域和具有高电压型栅极图案，低电压型栅极图案和电阻器图案的外围区域。 为了制造上述存储器件，在衬底中形成器件隔离层。 分别在周边区域的低压区域和高压区域形成具有差的厚度的栅极绝缘层。 在周边区域的栅极绝缘层的基本上整个表面上形成第一导电层。 在包括第一导电层的基板的基本上整个表面上顺序地形成包括隧道绝缘层，电荷存储层和阻挡绝缘层和第二导电层的三层。

公开(公告)号：US20060151824A1

公开(公告)日：2006-07-13

申请号：US11371379

申请日：2006-03-09

Applicant: Chang-Hyun Lee ,  Dong-Gun Park

Inventor： Chang-Hyun Lee ,  Dong-Gun Park

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

Abstract: Flash memory devices are provided including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.

Abstract translation: 在集成电路基板上提供包括集成电路基板和堆叠栅极结构的闪存器件。 沟槽隔离区域设置在与堆叠栅极结构相邻的集成电路基板上。 与沟槽隔离区的沟槽侧壁相邻的堆叠栅极结构的一部分可以包括第一氮掺杂层。