公开(公告)号：US20210183711A1

公开(公告)日：2021-06-17

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20210181775A1

公开(公告)日：2021-06-17

申请号：US17123299

申请日：2020-12-16

Applicant: IMEC VZW

Inventor： Nereo Markulic ,  Benjamin Hershberg ,  Jorge Luis Lagos Benites ,  Ewout Martens ,  Jan Craninckx

IPC: G05F1/565 ,  G05F1/46

Abstract: A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

公开(公告)号：US11038039B2

公开(公告)日：2021-06-15

申请号：US16675588

申请日：2019-11-06

Applicant: IMEC vzw

Inventor： Doyoung Jang ,  Min-Soo Kim

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: In one aspect, a method of forming a semiconductor device includes removing a first dummy gate part extending across a first fin within a first gate trench section in an insulating layer, wherein the first dummy gate part is removed selectively to a second dummy gate part extending across a second fin within a second gate trench section in the insulating layer, and wherein each of the first and second fins is formed by a layer stack including a first layer and a second layer on the first layer, the first layer including Si1-xGex and the second layer including Si1-yGey, wherein 0≤x≤1 and 0≤y≤1 and x≠y. The method includes forming a silicon capping layer on a portion of the first fin exposed in the first gate trench section, performing an oxidation process to oxidize the silicon capping layer and to oxidize an outer thickness portion of the portion of the first fin such that a trimmed fin portion including laterally trimmed first and second layer portions remains inside the oxidized outer thickness portion, and subsequent to performing the oxidation process, removing the second dummy gate while the oxidized silicon capping layer and the oxidized outer thickness portion covers the trimmed fin portion. The method also includes removing the oxidized silicon capping layer and the oxidized outer thickness portion from the trimmed fin portion, removing the laterally trimmed first layer portion exposed in the first gate trench section and a first layer portion exposed in the second gate trench section, and forming a final gate structure around the laterally trimmed second layer portion in the first gate trench section and around a second layer portion in the second gate trench section.

公开(公告)号：US20210174982A1

公开(公告)日：2021-06-10

申请号：US16616804

申请日：2018-07-10

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Stanislaw Piotr Zankowski ,  Philippe M. Vereecken

IPC: H01B1/02 ,  H01B5/00 ,  C25D1/08 ,  C25D11/18 ,  C25D11/04 ,  C23F1/20 ,  C25D11/02

Abstract: Porous solid materials are provided. The porous solid materials include a plurality of interconnected wires forming an ordered network. The porous solid materials may have a predetermined volumetric surface area ranging between 2 m2/cm3 and 90 m2/cm3, a predetermined porosity ranging between 3% and 90% and an electrical conductivity higher than 100 S/cm. The porous solid materials may have a predetermined volumetric surface area ranging between 3 m2/cm3 and 72 m2/cm3, a predetermined porosity ranging between 80% and 95% and an electrical conductivity higher than 100 S/cm. The porous solid materials (100) may have a predetermined volumetric surface area ranging between 3 m2/cm3 and 85 m2/cm3, a predetermined porosity ranging between 65% and 90% and an electrical conductivity higher than 2000 S/cm. Methods for the fabrication of such porous solid materials and devices including such porous solid material are also disclosed.

公开(公告)号：US11031253B2

公开(公告)日：2021-06-08

申请号：US16574902

申请日：2019-09-18

Applicant: IMEC VZW

Inventor： Quoc Toan Le ,  Henricus Philipsen ,  Frank Holsteyns

IPC: H01L21/3213 ,  H01L21/311

Abstract: A method for etching one or more entities on a semiconductor structure, each entity being made of a material selected from metals and metal nitrides is provided. The method includes the steps of: (a) oxidizing by electrolysis, at a current of at least 0.1 A, a precursor solution comprising chloride anions at a concentration ranging from 0.01 mol/l to 1.0 mol/l, thereby forming an etching solution; (b) providing a semiconductor structure having the one or more entities thereon; and (c) etching at least partially the one or more entities by contacting them with the etching solution.

公开(公告)号：US20210165546A1

公开(公告)日：2021-06-03

申请号：US17104844

申请日：2020-11-25

Applicant: IMEC VZW

Inventor： Alexandre Halbach ,  Veronique Rochus

IPC: G06F3/041 ,  G06F3/01 ,  G06F3/043 ,  H04M1/02

Abstract: A phased array ultrasound device includes transducer elements arranged in a two dimensional array; first electrodes, each first electrode extending along a first direction; and second electrodes, each second electrode extending along a second direction, where each transducer element is associated with one first electrode and one second electrode, where each transducer element includes a material located between its associated first electrode and second electrode, and is configured to emit an ultrasonic wave induced by a vibration force or an oscillation force of its material when the transducer element is actuated based on control signals applied to its associated first electrode and second electrode, where each transducer element has a unipolar actuation force direction, and where the phased array ultrasound device is configured to create a pressure focus point by actuating a set of transducer elements to form a combined ultrasonic wave.

公开(公告)号：US11018235B2

公开(公告)日：2021-05-25

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L27/11 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/06 ,  H01L29/417

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US11016022B2

公开(公告)日：2021-05-25

申请号：US16713549

申请日：2019-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Abdulkadir Yurt ,  Jasper Marien ,  Andy Lambrechts

IPC: G01N21/31 ,  G02B21/16 ,  G02B21/36 ,  G06T7/00 ,  H04N5/225

Abstract: A multimodal imaging system comprises a light source, an image sensor comprising a plurality of pixels, and an optical filter comprising a first filter element and a second filter element. The light source emits partially coherent polarized light, and the first filter element and second filter element are arranged as an array parallel to the image sensor. The first filter element is configured for attenuated transmission of a first light spectrum, which comprises polarized light emitted by the light source, and the second filter element is configured for transmission of a second light spectrum. The image sensor is configured to simultaneously capture light impinging on the image sensor from both the first filter element and the second filter element. Each filter element of the optical filter is configured for transmission of light to a subset of the imager pixels.

公开(公告)号：US20210152197A1

公开(公告)日：2021-05-20

申请号：US17098178

申请日：2020-11-13

Applicant: IMEC vzw ,  Vrije Universiteit Brussel

Inventor： Johan Nguyen ,  Khaled Khalaf ,  Pierre Wambacq ,  Jan Craninckx

IPC: H04B1/04 ,  H03F3/193

Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

公开(公告)号：US11012628B2

公开(公告)日：2021-05-18

申请号：US16677184

申请日：2019-11-07

Applicant: IMEC VZW

Inventor： Maarten Rosmeulen ,  Pierre Boulenc ,  Piet De Moor

IPC: H04N5/225 ,  H04N5/232 ,  H04N5/235

Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.