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    Method of forming a semiconductor device
    1.
    发明授权
    Method of forming a semiconductor device 有权

    公开(公告)号：US11038039B2

    公开(公告)日：2021-06-15

    申请号：US16675588

    申请日：2019-11-06

    Applicant: IMEC vzw

    Inventor： Doyoung Jang ,  Min-Soo Kim

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

    Abstract: In one aspect, a method of forming a semiconductor device includes removing a first dummy gate part extending across a first fin within a first gate trench section in an insulating layer, wherein the first dummy gate part is removed selectively to a second dummy gate part extending across a second fin within a second gate trench section in the insulating layer, and wherein each of the first and second fins is formed by a layer stack including a first layer and a second layer on the first layer, the first layer including Si1-xGex and the second layer including Si1-yGey, wherein 0≤x≤1 and 0≤y≤1 and x≠y. The method includes forming a silicon capping layer on a portion of the first fin exposed in the first gate trench section, performing an oxidation process to oxidize the silicon capping layer and to oxidize an outer thickness portion of the portion of the first fin such that a trimmed fin portion including laterally trimmed first and second layer portions remains inside the oxidized outer thickness portion, and subsequent to performing the oxidation process, removing the second dummy gate while the oxidized silicon capping layer and the oxidized outer thickness portion covers the trimmed fin portion. The method also includes removing the oxidized silicon capping layer and the oxidized outer thickness portion from the trimmed fin portion, removing the laterally trimmed first layer portion exposed in the first gate trench section and a first layer portion exposed in the second gate trench section, and forming a final gate structure around the laterally trimmed second layer portion in the first gate trench section and around a second layer portion in the second gate trench section.

    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure
    4.
    发明申请
    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure 有权
    形成包括鳍形通道结构的晶体管结构的方法

    公开(公告)号：US20160126131A1

    公开(公告)日：2016-05-05

    申请号：US14924832

    申请日：2015-10-28

    Applicant: IMEC VZW

    Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

    IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

    CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

    Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

    METHOD OF FORMING A SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200152770A1

    公开(公告)日：2020-05-14

    申请号：US16675588

    申请日：2019-11-06

    Applicant: IMEC vzw

    Inventor： Doyoung Jang ,  Min-Soo Kim

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

    Abstract: In one aspect, a method of forming a semiconductor device includes removing a first dummy gate part extending across a first fin within a first gate trench section in an insulating layer, wherein the first dummy gate part is removed selectively to a second dummy gate part extending across a second fin within a second gate trench section in the insulating layer, and wherein each of the first and second fins is formed by a layer stack including a first layer and a second layer on the first layer, the first layer including Si1-xGex and the second layer including Si1-yGey, wherein 0≤x≤1 and 0≤y≤1 and x≠y. The method includes forming a silicon capping layer on a portion of the first fin exposed in the first gate trench section, performing an oxidation process to oxidize the silicon capping layer and to oxidize an outer thickness portion of the portion of the first fin such that a trimmed fin portion including laterally trimmed first and second layer portions remains inside the oxidized outer thickness portion, and subsequent to performing the oxidation process, removing the second dummy gate while the oxidized silicon capping layer and the oxidized outer thickness portion covers the trimmed fin portion. The method also includes removing the oxidized silicon capping layer and the oxidized outer thickness portion from the trimmed fin portion, removing the laterally trimmed first layer portion exposed in the first gate trench section and a first layer portion exposed in the second gate trench section, and forming a final gate structure around the laterally trimmed second layer portion in the first gate trench section and around a second layer portion in the second gate trench section.

    Method for manufacturing a field effect transistor of a non-planar type
    8.
    发明授权
    Method for manufacturing a field effect transistor of a non-planar type 有权
    制造非平面型场效应晶体管的方法

    公开(公告)号：US09105746B2

    公开(公告)日：2015-08-11

    申请号：US14521083

    申请日：2014-10-22

    Applicant: IMEC VZW

    Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

    IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10

    CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

    Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

    Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

    Method for Manufacturing a Field Effect Transistor of a Non-Planar Type
    9.
    发明申请
    Method for Manufacturing a Field Effect Transistor of a Non-Planar Type 有权
    非平面型场效应晶体管的制造方法

    公开(公告)号：US20150111351A1

    公开(公告)日：2015-04-23

    申请号：US14521083

    申请日：2014-10-22

    Applicant: IMEC VZW

    Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

    IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

    Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

    Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

    Method and Structure for Determining an Overlay Error
    10.
    发明公开
    Method and Structure for Determining an Overlay Error 审中-公开

    公开(公告)号：US20230207482A1

    公开(公告)日：2023-06-29

    申请号：US18068839

    申请日：2022-12-20

    Applicant: IMEC VZW

    Inventor： Waikin Li ,  Zheng Tao ,  Min-Soo Kim

    IPC: H01L23/544 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L21/66

    CPC classification number: H01L23/544 ,  H01L29/7827 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0669 ,  H01L22/20

    Abstract: A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

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