-
公开(公告)号：US20250077411A1
公开(公告)日：2025-03-06
申请号：US18954112
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： David A. Roberts
IPC: G06F12/02 , G06F12/0882 , G06F13/16
Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
-
公开(公告)号：US20250077369A1
公开(公告)日：2025-03-06
申请号：US18750144
申请日：2024-06-21
Applicant: Micron Technology, Inc.
Inventor： Craig William Warner , Tony M. Brewer
Abstract: Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.
-
公开(公告)号：US20250077345A1
公开(公告)日：2025-03-06
申请号：US18775974
申请日：2024-07-17
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Joseph G. Garofalo
IPC: G06F11/10
Abstract: Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.
-
公开(公告)号：US20250077126A1
公开(公告)日：2025-03-06
申请号：US18951446
申请日：2024-11-18
Applicant: Micron Technology, Inc.
Inventor： Sahil Soi , Dhananjayan Athiyappan
IPC: G06F3/06
Abstract: A processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. Responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. The host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.
-
公开(公告)号：US20250077103A1
公开(公告)日：2025-03-06
申请号：US18745877
申请日：2024-06-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
IPC: G06F3/06
Abstract: Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.
-
Patent Agency Ranking
公开(公告)号：US20250077087A1
公开(公告)日：2025-03-06
申请号：US18954404
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： Luca Bert
Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.
-
公开(公告)号：US12245438B2
公开(公告)日：2025-03-04
申请号：US17656287
申请日：2022-03-24
Applicant: Micron Technology, Inc.
Inventor： Stephen W. Russell , Enrico Varesi , David H. Wells , Paolo Fantini , Lorenzo Fratin
Abstract: Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.
-
公开(公告)号：US12243620B2
公开(公告)日：2025-03-04
申请号：US18053626
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Mithun Kumar Ramasahayam , Michael J. Gossman
Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
-
公开(公告)号：US12243579B2
公开(公告)日：2025-03-04
申请号：US17819724
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Yuko Watanabe , Takefumi Shirako
IPC: G11C11/4091
Abstract: Electrically conductive line side-by-side running distance equalization and related apparatuses and systems. An apparatus includes a first sense amplifier, a second sense amplifier, a first pair of lines, and a second pair of lines. The first sense amplifier includes a first pull-up sense amplifier and a first pull-down sense amplifier. The first pair of lines electrically connects a first pull-up sense amplifier of the first sense amplifier to a first pull-down sense amplifier of the first sense amplifier. The second pair of lines electrically connects the second pull-up sense amplifier to the second pull-down sense amplifier. Parallel running distances between lines of the first pair of lines and the second pair of lines are equalized by a wiring twist of the first pair of lines and three wiring twists of the second pair of lines.
-
公开(公告)号：US12242884B2
公开(公告)日：2025-03-04
申请号：US17402849
申请日：2021-08-16
Applicant: Micron Technology, Inc.
Inventor： Douglas Vanesko , Bryan Hornung
Abstract: Various examples are directed to systems and methods for performing operations in a reconfigurable compute fabric. A dispatch interface may send a first asynchronous message to a first flow controller of a first synchronous flow. The first asynchronous message may instruct the first flow controller to begin execution of a first-level loop. The first synchronous flow may send a second asynchronous message to a second flow controller of a second synchronous flow. The second asynchronous message may instruct the second flow controller to execute a second-level loop. The first flow controller may receive a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop.
-
-
-
-
-
-
-
-
-
Search Results
32796
records
(took 0.075 seconds)
