Abstract:
An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes an array substrate provided with a plurality of sub-pixels, and a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and independent of each other, and a plurality of touch lines connecting the self capacitive electrodes to the touch detection chip; the plurality of gate lines and the plurality of data lines are intersected with each other to define the plurality of sub-pixels; each of the sub-pixels includes a pixel electrode and is configured with a long side and a short side; and the touch lines are disposed along the direction of short sides of the sub-pixels.
Abstract:
An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes: an upper substrate and a lower substrate arranged opposite to each other, a plurality of mutually independent self-capacitance electrodes arranged in the same layer, and a plurality of leads configured to connect the self-capacitance electrodes to a touch detection chip. The self-capacitance electrodes and the plurality of leads are arranged in different layers; an interlayer insulating layer is disposed between the self-capacitance electrodes and the leads; each self-capacitance electrode is electrically connected with the lead via a through hole running through the interlayer insulating layer; and the interlayer insulating layer is provided with recessed portions at overlapped areas of the self-capacitance electrodes and the leads other than the leads electrically connected with the self-capacitance electrodes. Therefore, the uniformity of display images of the touch panel can be improved.
Abstract:
An array substrate, a touch panel and a manufacturing method of an array substrate are provided. The array substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a common electrode layer and a plurality of pixel units arranged in an array disposed on the base substrate. Each of the pixel units includes a plurality of sub-pixel units defined by gate lines and data lines disposed to intersect each other laterally and vertically. The common electrode layer includes a plurality of common electrode blocks that double as self-capacitance electrodes, each of the common electrode blocks is connected with at least one wire, and the wires are in the middle of sub-pixel units of a same column. The array substrate is configured to increase aperture ratio of pixel units.
Abstract:
The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display apparatus. The array substrate comprises: a base substrate; and a pixel region and a periphery region formed on the base substrate, wherein the periphery region is located around the pixel region, the pixel region comprises an amorphous silicon thin film transistor, and the periphery region comprises a low temperature poly-silicon structure. As the a-Si thin film transistor is used in the pixel region of the array substrate, the problem that there is a too large leakage current in the pixel region of the LTPS array substrate in the prior art is overcome, the leakage current in the pixel region is reduced, while as the LTPS structure is used in the periphery region of the array substrate, a narrow frame of the display panel and the display apparatus may be achieved.
Abstract:
An array substrate is provided comprising a base substrate; an array of pixel electrodes formed on the base substrate; a plurality of gate lines, each of which is formed corresponding to each row of pixel electrodes; a plurality of data lines, each of which is formed corresponding to each odd number column of pixel electrodes and the next adjacent even number column of pixel electrodes; a plurality of first switching devices, each of which is connected with each odd-number-column pixel electrode, and the data lines charging the corresponding odd-number-column pixel electrodes via the corresponding first switching devices under driving control in corresponding time sequence; a plurality of second switching devices, each of which is connected with each even-number-column pixel electrode, and the data lines charging the corresponding even-number-column pixel electrodes via the corresponding second switching devices under driving control in corresponding time sequence.
Abstract:
The present invention provides a touch LCM comprising an array substrate and a color film substrate provided opposite to each other, wherein an optical film set is provided at a side of the color film substrate away from the array substrate, comprising a touch signal feedback layer, a touch signal receiving layer and an upper polarizer film provided there between. With the design of integrating the upper polarizer film, the touch signal feedback layer and the touch signal receiving layer into the optical film set, the optical film set has both the polarizing function in the conventional sense and the function of touch electrode.
Abstract:
An array substrate, a display device and a control method thereof are disclosed. The array substrate includes a plurality of gate lines and a plurality of data lines which are intercrossed to define pixels arranged in an array. The gate lines include n gate line groups and n+1 main gate lines; each gate line group includes a first gate line and a second gate line which are adjacent to each other; the first gate line is provided corresponding to a first transistor, and the second gate line is provided corresponding to a second transistor and a switching element; both the first gate line and the second gate line in the ith gate line group are connected with the ith main gate line; a gate electrode of the first transistor is connected with the first gate line, a source electrode connected with a corresponding data line, a drain electrode connected with a pixel electrode; a gate electrode of the second transistor is connected with one end of the switching element in a pixel unit, a source electrode connected with a corresponding data line, a drain electrode connected with a pixel electrode; and the other end of the switching element is connected with a main gate line in the (i+1)th row and configured to control on/off operation of the second transistor.