公开(公告)号：US11870163B2

公开(公告)日：2024-01-09

申请号：US17705182

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Robert L. Sankman ,  Shawna M. Liff ,  Sri Chaitra Jyotsna Chavali ,  William J. Lambert ,  Zhichao Zhang

IPC: H01Q9/04 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01Q9/0414 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US11769751B2

公开(公告)日：2023-09-26

申请号：US16649949

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L25/065 ,  H01L23/5383 ,  H01L23/5389

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a transmitter/receiver logic (TRL) die coupled to the first surface of the package substrate; a plurality of antenna elements adjacent the second surface of the package substrate; and a transmitter/receiver chain (TRC) die, wherein the TRC die is embedded in the package substrate, and wherein the TRC die is electrically coupled to the RF die and at least one of the plurality of antenna elements via conductive pathways in the package substrate. In some embodiments, a microelectronic assembly may further include a double-sided TRC die. In some embodiments, a microelectronic assembly may further include a TRC die having an amplifier. In some embodiments, a microelectronic assembly may further include a TRL die having a modem and a phase shifter.

公开(公告)号：US11756943B2

公开(公告)日：2023-09-12

申请号：US16650698

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L25/16 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L23/538 ,  H01L27/14 ,  G02B6/42 ,  G02B6/43 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/167 ,  G02B6/4206 ,  G02B6/43 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/071 ,  H01L25/112 ,  H01L2224/214

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die.

公开(公告)号：US20230178513A1

公开(公告)日：2023-06-08

申请号：US17543419

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Georgios Dogiamis ,  Bradley A. Jackson ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/50 ,  H01L24/80 ,  H01L24/96 ,  H01L24/16 ,  H01L2225/06572 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.

公开(公告)号：US11616047B2

公开(公告)日：2023-03-28

申请号：US17129221

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

公开(公告)号：US20230073026A1

公开(公告)日：2023-03-09

申请号：US17470189

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Han Wui Then

IPC: H01L23/528 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.

公开(公告)号：US20230018902A1

公开(公告)日：2023-01-19

申请号：US17956773

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US11527501B1

公开(公告)日：2022-12-13

申请号：US17122934

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Veronica Aleman Strong ,  Shawna M. Liff ,  Brandon M. Rawlings ,  Jagat Shakya ,  Johanna M. Swan ,  David M. Craig ,  Jeremy Alan Streifer ,  Brennen Karl Mueller

IPC: H01L23/00 ,  H01L21/18 ,  B81B7/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

公开(公告)号：US11508587B2

公开(公告)日：2022-11-22

申请号：US16648645

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L21/48 ,  H01L23/538 ,  H01L29/66 ,  H05K3/30

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

公开(公告)号：US11494682B2

公开(公告)日：2022-11-08

申请号：US16766411

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/06 ,  G06N10/00 ,  H01L21/48 ,  H01L27/18 ,  H01L39/02 ,  H01L39/24 ,  B82Y10/00

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.