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21 条记录 (耗时 0.017 秒)

    Segmentation, handshaking, and access control solutions for Opendots technology
    4.
    发明授权
    Segmentation, handshaking, and access control solutions for Opendots technology 有权

    公开(公告)号：US09985958B2

    公开(公告)日：2018-05-29

    申请号：US15081883

    申请日：2016-03-26

    申请人： Intel Corporation

    发明人： Bo Qiu ,  Jianfang Zhu ,  Anand S. Konanur ,  Bradley A. Jackson ,  Sayan Lahiri

    IPC分类号： H02J7/00 ,  H04L29/06 ,  H04W12/06

    CPC分类号： H04L63/083 ,  H04W12/06

    摘要： Apparatus, methods, and systems described herein are for segmentation, handshaking, and access control solutions for Opendots technology. One embodiment described a charging pad that includes a plurality of conductive strips, switches, and decipher circuitry. A switch is coupled to the plurality of conductive strips whereas the decipher circuitry is coupled to the plurality of conductive strips and the switch. In response to contact with one conductive strip of the plurality of conductive strips, the decipher circuitry determines whether a security password has been received. The switch allows a voltage higher than a threshold voltage level to be supplied to an external device if the security password is received by the decipher circuitry. However, the switch can also prevent a voltage higher than a threshold voltage level to be supplied to an external device if the security password is not received by the decipher circuitry.

    NEAR MEMORY SPARSE MATRIX COMPUTATION IN DEEP NEURAL NETWORK
    6.
    发明申请
    NEAR MEMORY SPARSE MATRIX COMPUTATION IN DEEP NEURAL NETWORK 有权

    公开(公告)号：US20220101091A1

    公开(公告)日：2022-03-31

    申请号：US17550405

    申请日：2021-12-14

    申请人： Intel Corporation

    发明人： Srivatsa Rangachar Srinivasa ,  Jainaveen Sundaram Priya ,  Bradley A. Jackson ,  Ambili Vengallur ,  Dileep John Kurian ,  Tanay Karnik

    IPC分类号： G06N3/04 ,  G06N3/063 ,  G06F7/523 ,  G06F7/50

    摘要： A DNN accelerator includes a multiplication controller controlling whether to perform matrix computation based on weight values. The multiplication controller reads a weight matrix from a WRAM in the DNN accelerator and determines a row value for a row in the weight matrix. In an embodiment where the row value is one, a first switch sends a read request to the WRAM to read weights in the row and a second switch forms a data transmission path from an IRAM in the DNN accelerator to a PE in the DNN accelerator. The PE receives the weights and input data stored in the IRAM and performs MAC operations. In an embodiment where the row value is zero, the first and second switches are not triggered. No read request is sent to the WRAM and the data transmission path is not formed. The PE will not perform any MAC operations.