公开(公告)号：US08188765B2

公开(公告)日：2012-05-29

申请号：US12882425

申请日：2010-09-15

申请人： Michael R. Ouellette ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Michael R. Ouellette ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03K19/00 ,  H03K19/096 ,  H03K19/094 ,  H03K19/20

CPC分类号： G06F5/10 ,  G06F2205/104

摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.

摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。

公开(公告)号：US08174329B2

公开(公告)日：2012-05-08

申请号：US12787167

申请日：2010-05-25

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： H03K3/03 ,  H03L5/02

CPC分类号： H03K3/0315

摘要： A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 一种基于电压源调制逻辑时钟振荡器频率的方法和系统。 该系统包括具有逻辑操作的逻辑单元和用于产生自适应时钟以匹配逻辑运算的装置。 该器件被配置为使用电源电压作为独立变量来优化电压变化的器件参数。 本发明还涉及电路所在的设计结构。

公开(公告)号：US07966589B2

公开(公告)日：2011-06-21

申请号：US12099423

申请日：2008-04-08

申请人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing D. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Welland

发明人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing D. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Welland

IPC分类号： G06F17/50

CPC分类号： G11C5/145 ,  H03K3/356008

摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

摘要翻译： 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

公开(公告)号：US07913193B2

公开(公告)日：2011-03-22

申请号：US11924935

申请日：2007-10-26

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F17/50

CPC分类号： G06F12/121 ,  G06F2212/1056 ,  G11C7/1006

摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电荷存储装置，其耦合到数据保持装置，使得数据保持装置的使用触发电荷源对电荷存储装置的充电; 以及用于测量电荷存储装置的电位的装置，所述测量装置通信地耦合到基于所测量的电位确定数据保持装置的相对使用量的计算平均值。

公开(公告)号：US07873961B2

公开(公告)日：2011-01-18

申请号：US11161330

申请日：2005-07-29

申请人： Laura F Miller ,  Nancy H. Pratt ,  Sebastian T. Ventrone

发明人： Laura F Miller ,  Nancy H. Pratt ,  Sebastian T. Ventrone

IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F12/00

CPC分类号： G06F9/462 ,  G06F9/4843

摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及能够分派指令和附加到指令的标签的调度器，识别操作系统之一的标签和在所识别的操作系统下执行的指令以访问寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。

公开(公告)号：US07869298B2

公开(公告)日：2011-01-11

申请号：US12045744

申请日：2008-03-11

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F12/122

摘要： A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

摘要翻译： 公开了一种用于确定数据保持装置的相对使用量的系统。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

公开(公告)号：US07761690B2

公开(公告)日：2010-07-20

申请号：US11828705

申请日：2007-07-26

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/48

CPC分类号： G06F9/3836 ,  G06F9/3897 ,  G06F15/7867

摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。

公开(公告)号：US07644327B2

公开(公告)日：2010-01-05

申请号：US12049166

申请日：2008-03-14

申请人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： John M. Cohn ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  G01R31/318558 ,  G06F11/261 ,  H03K19/00392

摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.

摘要翻译： 一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。 该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。 如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。 识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。 识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

公开(公告)号：US07633819B2

公开(公告)日：2009-12-15

申请号：US12180776

申请日：2008-07-28

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C29/00

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

公开(公告)号：US20090302889A1

公开(公告)日：2009-12-10

申请号：US12135249

申请日：2008-06-09

申请人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

发明人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

IPC分类号： H03K19/0175

CPC分类号： H03K19/0008 ,  H03K19/173

摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.

摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。