公开(公告)号：US06450647B1

公开(公告)日：2002-09-17

申请号：US09640982

申请日：2000-08-18

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G03B2100

CPC classification number: H04N9/3185 ,  H04N5/74 ,  H04N2005/745

Abstract: A display pixel range between a display start position and a display end position of a distortion corrected image is determined on each horizontal line of the image forming section, based on horizontal correction parameters representing distortion-correction amounts at left- and right-sides of the distortion-corrected image to be supplied to an image forming section for forming an image to be projected onto a screen, and a first relation between each pixel within the display pixel range and each pixel in the original image is determined. A display line range between a display start line and a display end line of the distortion corrected image is also determined on the image forming section, based on vertical correction parameters representing distortion-correction amounts in the vertical direction of the distortion-corrected image, a second relation between each line within the display line range and each line in the original image is determined. The distortion-corrected image is produced from the original image according to the first and second relations. This allows easy correction of image distortion due to tilt projection of images onto the screen.

Abstract translation: 基于表示在图像形成部的左右两侧的失真校正量的水平校正参数，在图像形成部的每条水平线上确定失真校正图像的显示开始位置和显示结束位置之间的显示像素范围 将被提供给图像形成部分的失真校正图像用于形成要投影到屏幕上的图像，并且确定显示像素范围内的每个像素与原始图像中的每个像素之间的第一关系。 还根据表示失真校正图像的垂直方向上的失真校正量的垂直校正参数，在图像形成部分确定显示起始行和失真校正图像的显示结束行之间的显示行范围， 确定显示行范围内的各行与原始图像中的每一行之间的第二关系。 根据第一和第二关系从原始图像产生失真校正图像。 这允许容易地校正由于图像在屏幕上的倾斜投影引起的图像失真。

公开(公告)号：US06239729B1

公开(公告)日：2001-05-29

申请号：US09341696

申请日：1999-07-26

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H03M900

CPC classification number: G09G5/008 ,  G09G5/006 ,  G09G5/395 ,  G09G2360/02

Abstract: A digital image signal is latched by four latches respectively in response to four latch clock signs, which have a frequency that is ¼ of a frequency of a dot clock signal and phases that are mutually shifted by every period of the dot dock signal. The four latched digital image signals are further latched by a common latch in response to a common latch signal. The digital image signals with respect to four consecutive pixels are then output as one set of digital image signals. The output digital image signals are written into consecutive storage areas in a frame memory, in response to a write sampling dock signal which has a frequency that is ¼ of the frequency of the dot clock signal The number of latches is regulated according to a frequency of an analog image signal. This arrangement facilitates image processing for high-frequency image signals.

Abstract translation: 数字图像信号分别响应于四个锁存时钟符号被锁存，四个锁存时钟符号的频率是点时钟信号的频率的1/4，并且由点对点信号的每个周期相互移位的相位。 响应于公共锁存信号，四个锁存的数字图像信号被公共锁存器进一步锁存。 然后将相对于四个连续像素的数字图像信号作为一组数字图像信号输出。 输出数字图像信号被写入到帧存储器中的连续存储区域中，响应于具有为点时钟信号的频率的1/4的频率的写取样停靠信号。锁存器的数量根据 模拟图像信号。 这种布置方便了高频图像信号的图像处理。

公开(公告)号：US5929933A

公开(公告)日：1999-07-27

申请号：US802766

申请日：1997-02-20

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F3/14 ,  G06T11/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  H04N5/262 ,  H04N5/265 ,  H04N5/278 ,  H04N9/64 ,  H04N5/44 ,  G09G5/00 ,  H04N9/74

CPC classification number: H04N9/641 ,  G09G5/14 ,  G09G5/366 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N21/4143 ,  H04N5/44 ,  H04N5/44504 ,  H04N5/44591 ,  H04N5/45 ,  G09G2340/045 ,  G09G2340/125 ,  G09G2360/126 ,  G09G5/026 ,  G09G5/393 ,  H04N5/4401

Abstract: An image control device for use in the computer system. The computer system includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. Writing of an image system signal into the video memory is controlled by supplying a first write address to the video memory. Reading of an image signal out of the video memory is controlled by supplying a read address to the video memory. The operation of reading the image signal out of the video memory independently changes a display part and a magnification of an image represented by the image signal read out of the video memory so that the display part of the image is displayed by the magnification on the display device.

Abstract translation: 一种用于计算机系统中的图像控制装置。 计算机系统包括微处理器，耦合到微处理器的总线，耦合到总线的视频存储器和显示设备。 通过向视频存储器提供第一写入地址来控制将图像系统信号写入视频存储器。 通过向视频存储器提供读取地址来控制从视频存储器读出图像信号。 从视频存储器读出图像信号的操作独立地改变由从视频存储器读出的图像信号表示的图像的显示部分和放大率，使得通过显示器上的倍率显示图像的显示部分 设备。

公开(公告)号：US5880741A

公开(公告)日：1999-03-09

申请号：US960270

申请日：1997-10-29

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F13/28 ,  G06T1/00 ,  G06T1/60 ,  G06T3/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/377 ,  G09G5/393 ,  H04N5/907 ,  H04N5/92 ,  G06T11/00

CPC classification number: G09G5/393 ,  G09G2320/0261

Abstract: A mask data RAM (Random Access Memory) 213 stores mask data TDATA, which is 1 bit dot data representing a moving picture area MR. The state of the mask data TDATA determines the level of a write signal /MWR given to a dual-port VRAM (Video Random Access Memory) 212 for storing video data. An address for DMA (Direct Memory Access) transfer of the video data to the dual-port VRAM 212 is given to the mask data RAM 213 as well as the dual-port VRAM 212, and therefore the mask data TDATA are read out from the mask data RAM 213 for each dot of the video data. The mask data TDATA are updated according to the position and the shape of a moving picture window on a display screen. This allows a moving picture of an arbitrary shape corresponding to the state of the moving picture window to be transferred to the dual-port VRAM 212 and displayed on the display device.

Abstract translation: 掩模数据RAM（随机存取存储器）213存储作为表示运动图像区域MR的1位点数据的掩模数据TDATA。 掩模数据TDATA的状态确定给予用于存储视频数据的双端口VRAM（视频随机存取存储器）212的写入信号/ MWR的电平。 将视频数据的DMA（直接存储器访问）传送到双端口VRAM 212的地址被提供给掩模数据RAM 213以及双端口VRAM 212，并且因此从其中读出掩模数据TDATA 屏幕数据RAM 213，用于视频数据的每个点。 掩模数据TDATA根据显示屏幕上的运动图像窗口的位置和形状被更新。 这允许将与运动图像窗口的状态对应的任意形状的运动图像传送到双端口VRAM 212并显示在显示装置上。

公开(公告)号：US5546137A

公开(公告)日：1996-08-13

申请号：US389488

申请日：1995-02-16

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F13/28 ,  G06T1/60 ,  G09G5/02 ,  G09G5/393

CPC classification number: G06F13/28 ,  G09G5/022 ,  G09G5/393 ,  H04N19/00 ,  G09G2340/12

Abstract: A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.

公开(公告)号：US5185584A

公开(公告)日：1993-02-09

申请号：US620173

申请日：1990-11-30

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H03K3/03 ,  H03K3/354 ,  H03L7/099

CPC classification number: H03L7/099 ,  H03K3/03 ,  H03K3/354

Abstract: A phase locked loop (PLL) circuit comprises a phase comparator, a low-pass filter, an error amplifier, and a voltage controlled oscillator (VCO) circuit which includes a current mirror circuit section and oscillator circuit section to provide an oscillation frequency based on the output current of the current mirror circuit section. To vary the oscillation over a wide range, a fixed reference voltage circuit is connected to the current mirror circuit, and either a source follower circuit made of a MOSFET or a FET or an emitter follower circuit made of a bipolar transistor is included is also connected to the current mirror circuit to selectively varying the output current of the current mirror circuit section upon application of a control voltage applied to the follower circuit. Thus, the follower circuit is controlled by a control voltage while the output current of the current mirror circuit varies depending on the magnitude of the control voltage, and, in turn, the oscillating frequency of the oscillator circuit section varies over a wide frequency range, e.g., in excess of 100 dB, in accordance with the output current.

Abstract translation: 锁相环（PLL）电路包括相位比较器，低通滤波器，误差放大器和压控振荡器（VCO）电路，其包括电流镜电路部分和振荡器电路部分，以提供基于 电流镜电路部分的输出电流。 为了在宽范围内改变振荡，固定参考电压电路连接到电流镜电路，并且包括由MOSFET或FET制成的源极跟随器电路或由双极晶体管制成的射极跟随器电路也被连接 连接到电流镜电路，以在施加施加到跟随器电路的控制电压时选择性地改变电流镜电路部分的输出电流。 因此，跟随器电路由控制电压控制，而电流镜电路的输出电流根据控制电压的大小而变化，并且振荡器电路部分的振荡频率又在较宽的频率范围内变化， 例如，超过100dB，根据输出电流。

公开(公告)号：US08729769B2

公开(公告)日：2014-05-20

申请号：US13488961

申请日：2012-06-05

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H02K1/22

CPC classification number: H02K7/003 ,  B25J9/126 ,  B60L2220/50 ,  H02K1/278 ,  H02K1/30 ,  H02K7/116 ,  H02K15/00 ,  H02K15/03 ,  Y02T10/641 ,  Y10T29/49009

Abstract: An electromechanical device includes: a center shaft; a rotor having a rotor magnet disposed around an outer periphery of the center shaft; and a stator disposed on an outer periphery of the rotor, wherein the center shaft is formed of a carbon-fiber-reinforced plastic, and when projection is performed in a radial direction from the center shaft toward the rotor magnet, an angle between a direction of carbon fiber in the carbon-fiber-reinforced plastic and a direction of the center shaft is 45°.

Abstract translation: 机电装置包括：中心轴; 转子，其具有绕所述中心轴的外周配置的转子磁体; 以及设置在所述转子的外周上的定子，其中所述中心轴由碳纤维增强塑料形成，并且当从所述中心轴朝向所述转子磁体沿径向方向进行突起时，所述方向 碳纤维增强塑料中的碳纤维和中心轴的方向为45°。

公开(公告)号：US08654498B2

公开(公告)日：2014-02-18

申请号：US13371753

申请日：2012-02-13

Applicant: Kesatoshi Takeuchi ,  Katsuhiko Nishizawa

Inventor： Kesatoshi Takeuchi ,  Katsuhiko Nishizawa

IPC: H01H47/00

CPC classification number: B62M6/50 ,  G01K7/16

Abstract: An electromechanical device includes a rotor, a stator having a magnetic coil, a sensor adapted to detect an electric angle of the rotor, a control section adapted to perform a PWM drive on the magnetic coil based on a signal from the sensor, a resistor connected in series to the magnetic coil when measuring temperature of the electromechanical device, and a voltage measurement section adapted to measure a voltage between both ends of the resistor, and the control section calculates an electric resistance of the magnetic coil using the voltage between the both ends of the resistor measured by the voltage measurement section, and then determines the temperature of the magnetic coil using the electric resistance of the magnetic coil in a measurement period in which application of a drive voltage to the magnetic coil is stopped in the PWM drive.

Abstract translation: 机电装置包括转子，具有磁线圈的定子，适于检测转子电角的传感器，适于基于来自传感器的信号在磁线圈上执行PWM驱动的控制部分，连接有电阻器 在测量机电装置的温度时与电磁线圈串联连接的电压测量部以及适于测量电阻器两端的电压的电压测量部，控制部使用两端之间的电压来计算电磁线圈的电阻 由电压测量部测量的电阻，然后在PWM驱动中停止对磁性线圈施加驱动电压的测量周期内，使用电磁线圈的电阻来确定电磁线圈的温度。

公开(公告)号：US08344684B2

公开(公告)日：2013-01-01

申请号：US13012910

申请日：2011-01-25

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H02P7/29

CPC classification number: H02P6/16

Abstract: The circuit structured to drive a motor is provided. The circuit includes: a division signal generator that generates a division signal dividing each of a high level period and a low level period of a binary position signal representing a relative position of a magnetic coil to a permanent magnet into a preset number of multiple divisions; a pulse width setter that sets a pulse width for PWM control corresponding to each of the multiple divisions represented by the division signal; and a PWM signal generator that performs PWM control with the set pulse width, thereby generating a PWM signal as a driving signal for driving the motor.

Abstract translation: 提供了构造成驱动电动机的电路。 该电路包括：除法信号发生器，其将表示磁性线圈相对于永久磁铁的相对位置的二进制位置信号的高电平周期和低电平周期分割成预定数量的多个分割; 脉冲宽度设定器，其设定与由所述除法信号表示的所述多个分割中的每一个对应的PWM控制的脉冲宽度; PWM信号发生器，其以设定的脉冲宽度进行PWM控制，从而生成作为驱动马达的驱动信号的PWM信号。

公开(公告)号：US08314577B2

公开(公告)日：2012-11-20

申请号：US13455597

申请日：2012-04-25

Applicant: Kesatoshi Takeuchi ,  Kazuyoshi Nakamura

Inventor： Kesatoshi Takeuchi ,  Kazuyoshi Nakamura

IPC: H02P6/00

CPC classification number: H02P6/085 ,  H02P25/18 ,  H02P25/184 ,  H02P27/08

Abstract: An energy converter includes magnetic coils of N phases (N is an integer of 3 or more), and a PWM drive circuit for driving the magnetic coils of N phases, wherein the magnetic coil of each phase can be independently controlled by the PWM drive circuit.

Abstract translation: 能量转换器包括N相的磁性线圈（N为3以上的整数），以及用于驱动N相的磁性线圈的PWM驱动电路，其中，各相的磁线圈可以由PWM驱动电路独立地控制 。