Abstract:
A display pixel range between a display start position and a display end position of a distortion corrected image is determined on each horizontal line of the image forming section, based on horizontal correction parameters representing distortion-correction amounts at left- and right-sides of the distortion-corrected image to be supplied to an image forming section for forming an image to be projected onto a screen, and a first relation between each pixel within the display pixel range and each pixel in the original image is determined. A display line range between a display start line and a display end line of the distortion corrected image is also determined on the image forming section, based on vertical correction parameters representing distortion-correction amounts in the vertical direction of the distortion-corrected image, a second relation between each line within the display line range and each line in the original image is determined. The distortion-corrected image is produced from the original image according to the first and second relations. This allows easy correction of image distortion due to tilt projection of images onto the screen.
Abstract:
A digital image signal is latched by four latches respectively in response to four latch clock signs, which have a frequency that is ¼ of a frequency of a dot clock signal and phases that are mutually shifted by every period of the dot dock signal. The four latched digital image signals are further latched by a common latch in response to a common latch signal. The digital image signals with respect to four consecutive pixels are then output as one set of digital image signals. The output digital image signals are written into consecutive storage areas in a frame memory, in response to a write sampling dock signal which has a frequency that is ¼ of the frequency of the dot clock signal The number of latches is regulated according to a frequency of an analog image signal. This arrangement facilitates image processing for high-frequency image signals.
Abstract:
An image control device for use in the computer system. The computer system includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. Writing of an image system signal into the video memory is controlled by supplying a first write address to the video memory. Reading of an image signal out of the video memory is controlled by supplying a read address to the video memory. The operation of reading the image signal out of the video memory independently changes a display part and a magnification of an image represented by the image signal read out of the video memory so that the display part of the image is displayed by the magnification on the display device.
Abstract:
A mask data RAM (Random Access Memory) 213 stores mask data TDATA, which is 1 bit dot data representing a moving picture area MR. The state of the mask data TDATA determines the level of a write signal /MWR given to a dual-port VRAM (Video Random Access Memory) 212 for storing video data. An address for DMA (Direct Memory Access) transfer of the video data to the dual-port VRAM 212 is given to the mask data RAM 213 as well as the dual-port VRAM 212, and therefore the mask data TDATA are read out from the mask data RAM 213 for each dot of the video data. The mask data TDATA are updated according to the position and the shape of a moving picture window on a display screen. This allows a moving picture of an arbitrary shape corresponding to the state of the moving picture window to be transferred to the dual-port VRAM 212 and displayed on the display device.
Abstract:
A multiplier 7 multiplies an adding address stored in an adding address memory 3 by a vertical count output from a vertical counter unit 4. A first adder 8 adds the product of the multiplier 7 to an offset address stored in the offset address memory 2. A second adder 9 adds the sum in the first adder 8 to a horizontal count in a horizontal counter unit 5. A third adder 10 adds the sum in the second adder 9 to each of area-start addresses for RGB color components stored in three area-start address memory units 6R, 6G, and 6B, respectively. An output AD3 from the third adder 10 becomes an access address in DMA transfer. The access address in DMA transfer is accordingly calculated by simple arithmetic operation in a DMA controller 34, which thereby attains high-speed DMA transfer.
Abstract:
A phase locked loop (PLL) circuit comprises a phase comparator, a low-pass filter, an error amplifier, and a voltage controlled oscillator (VCO) circuit which includes a current mirror circuit section and oscillator circuit section to provide an oscillation frequency based on the output current of the current mirror circuit section. To vary the oscillation over a wide range, a fixed reference voltage circuit is connected to the current mirror circuit, and either a source follower circuit made of a MOSFET or a FET or an emitter follower circuit made of a bipolar transistor is included is also connected to the current mirror circuit to selectively varying the output current of the current mirror circuit section upon application of a control voltage applied to the follower circuit. Thus, the follower circuit is controlled by a control voltage while the output current of the current mirror circuit varies depending on the magnitude of the control voltage, and, in turn, the oscillating frequency of the oscillator circuit section varies over a wide frequency range, e.g., in excess of 100 dB, in accordance with the output current.
Abstract:
An electromechanical device includes: a center shaft; a rotor having a rotor magnet disposed around an outer periphery of the center shaft; and a stator disposed on an outer periphery of the rotor, wherein the center shaft is formed of a carbon-fiber-reinforced plastic, and when projection is performed in a radial direction from the center shaft toward the rotor magnet, an angle between a direction of carbon fiber in the carbon-fiber-reinforced plastic and a direction of the center shaft is 45°.
Abstract:
An electromechanical device includes a rotor, a stator having a magnetic coil, a sensor adapted to detect an electric angle of the rotor, a control section adapted to perform a PWM drive on the magnetic coil based on a signal from the sensor, a resistor connected in series to the magnetic coil when measuring temperature of the electromechanical device, and a voltage measurement section adapted to measure a voltage between both ends of the resistor, and the control section calculates an electric resistance of the magnetic coil using the voltage between the both ends of the resistor measured by the voltage measurement section, and then determines the temperature of the magnetic coil using the electric resistance of the magnetic coil in a measurement period in which application of a drive voltage to the magnetic coil is stopped in the PWM drive.
Abstract:
The circuit structured to drive a motor is provided. The circuit includes: a division signal generator that generates a division signal dividing each of a high level period and a low level period of a binary position signal representing a relative position of a magnetic coil to a permanent magnet into a preset number of multiple divisions; a pulse width setter that sets a pulse width for PWM control corresponding to each of the multiple divisions represented by the division signal; and a PWM signal generator that performs PWM control with the set pulse width, thereby generating a PWM signal as a driving signal for driving the motor.
Abstract:
An energy converter includes magnetic coils of N phases (N is an integer of 3 or more), and a PWM drive circuit for driving the magnetic coils of N phases, wherein the magnetic coil of each phase can be independently controlled by the PWM drive circuit.