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    THREE DIMENSIONAL MEMORY ARRAY
    151.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20180374897A1

    公开(公告)日：2018-12-27

    申请号：US16118632

    申请日：2018-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    Mixed cross point memory
    152.
    发明授权
    Mixed cross point memory 有权

    公开(公告)号：US10157667B2

    公开(公告)日：2018-12-18

    申请号：US15582321

    申请日：2017-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C5/06 ,  G11C13/00 ,  G11C11/56

    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.

    THREE DIMENSIONAL MEMORY ARRAY
    153.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20180294312A1

    公开(公告)日：2018-10-11

    申请号：US15482016

    申请日：2017-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    Constructions comprising stacked memory arrays
    159.
    发明授权
    Constructions comprising stacked memory arrays 有权

    公开(公告)号：US09881973B2

    公开(公告)日：2018-01-30

    申请号：US15607786

    申请日：2017-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

    Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.

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