公开(公告)号：US20150255575A1

公开(公告)日：2015-09-10

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。

公开(公告)号：US20250149378A1

公开(公告)日：2025-05-08

申请号：US19014922

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D86/00

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

公开(公告)号：US20250096041A1

公开(公告)日：2025-03-20

申请号：US18955171

申请日：2024-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US12255171B2

公开(公告)日：2025-03-18

申请号：US17412768

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/683

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10−2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

公开(公告)号：US12255101B2

公开(公告)日：2025-03-18

申请号：US18401780

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

公开(公告)号：US12230532B2

公开(公告)日：2025-02-18

申请号：US17459509

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

公开(公告)号：US12224327B2

公开(公告)日：2025-02-11

申请号：US18366369

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US12191174B2

公开(公告)日：2025-01-07

申请号：US17720807

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US20240395581A1

公开(公告)日：2024-11-28

申请号：US18790913

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US20240387445A1

公开(公告)日：2024-11-21

申请号：US18787709

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/683

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10−2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.