公开(公告)号：US11658053B2

公开(公告)日：2023-05-23

申请号：US16659090

申请日：2019-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael Raga-Barone

IPC: H01L21/677 ,  G03F7/20

CPC classification number: H01L21/67769 ,  G03F7/70741 ,  H01L21/67775

Abstract: One illustrative device disclosed herein includes a FOUP (Front Opening Unified Pod) storage bin, a plurality of pins positioned on a first surface of the FOUP storage bin, wherein the plurality of pins are adapted to engage and register with the FOUP, and a conversion plate. In one illustrative embodiment, the conversion plate includes a plate with a front surface and a back surface, a reticle pod receiving structure on the front surface that at least partially bounds a reticle pod receiving area on the front surface, and a pin engagement structure on the back side that is adapted to engage the plurality of pins on the first surface of the FOUP storage bin.

公开(公告)号：US11656409B2

公开(公告)日：2023-05-23

申请号：US17197133

申请日：2021-03-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Qizhi Liu

IPC: G02B6/124 ,  G02B6/13

CPC classification number: G02B6/124 ,  G02B6/13

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a semiconductor waveguide on a semiconductor layer. The semiconductor waveguide includes a first vertical sidewall over the semiconductor layer over the semiconductor layer. A plurality of grating protrusions extends horizontally from the first vertical sidewall of the semiconductor waveguide.

公开(公告)号：US20230147981A1

公开(公告)日：2023-05-11

申请号：US18149239

申请日：2023-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7606 ,  H01L29/0847 ,  H01L29/1033

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US20230130467A1

公开(公告)日：2023-04-27

申请号：US17452129

申请日：2021-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/30 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US11631759B2

公开(公告)日：2023-04-18

申请号：US17164855

申请日：2021-02-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Meng Miao ,  Alain François Loiseau ,  Souvick Mitra ,  Robert John Gauthier, Jr. ,  You Li ,  Wei Liang

IPC: H01L29/06 ,  H01L29/74 ,  H01L29/66

Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

公开(公告)号：US11630335B2

公开(公告)日：2023-04-18

申请号：US17170237

申请日：2021-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michal Rakowski ,  Abdelsalam Aboketaf ,  Kevin K. Dezfulian ,  Massimo Sorbara

IPC: G02F1/025 ,  G02F1/225

Abstract: Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A first waveguide core includes first and second sections. A second waveguide core includes a first section laterally adjacent to the first section of the first waveguide core and a second section laterally adjacent to the second section of the first waveguide core. An interconnect structure is formed over the first waveguide core and the second waveguide core. The interconnect structure includes first and second transmission lines. The first transmission line is physically connected within the interconnect structure to the first section of the first waveguide core. The second transmission line includes a first section physically connected within the interconnect structure to the second section of the first waveguide core and a second section adjacent to the first transmission line.

公开(公告)号：US20230113261A1

公开(公告)日：2023-04-13

申请号：US17450324

申请日：2021-10-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Roderick Alan Augur ,  Yusheng Bian ,  Robert John Fox, III

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/552

Abstract: A photonic integrated circuit (PIC) die includes a silicon nitride optical component over an active region. Multiple interconnect layers are over the silicon nitride optical component, each of the multiple interconnect layers including a metal interconnect therein. At least one optical deflector is over the multiple interconnect layers and over the silicon nitride optical component. The optical deflector(s) may also include a contact passing therethrough to the interconnect layers, but do not include any other electrical interconnects. Each optical deflector may deflect light within an ambient light range of less than 570 nanometers (nm) to protect the silicon nitride optical component from light-induced degradation.

公开(公告)号：US20230112235A1

公开(公告)日：2023-04-13

申请号：US17692517

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Shesh Mani Pandey

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

公开(公告)号：US20230098557A1

公开(公告)日：2023-03-30

申请号：US17578687

申请日：2022-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

公开(公告)号：US20230096328A1

公开(公告)日：2023-03-30

申请号：US17546200

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu ,  Alexander Derrickson

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L29/40 ,  H01L29/66

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.