公开(公告)号：US20120169332A1

公开(公告)日：2012-07-05

申请号：US13417399

申请日：2012-03-12

申请人： Po-Kang Wang ,  Xizeng Shi ,  Chyu-Jiuh Torng

发明人： Po-Kang Wang ,  Xizeng Shi ,  Chyu-Jiuh Torng

IPC分类号： G01R33/02 ,  B23P17/04

CPC分类号： G01R33/0052 ,  B82Y25/00 ,  G01N15/0656 ,  G01N27/745 ,  G01N2015/0065 ,  G01R33/05 ,  G01R33/093 ,  G01R33/098 ,  Y10T29/49124 ,  Y10T29/49986

摘要： A sensor array comprising a series connection of parallel GMR sensor stripes provides a sensitive mechanism for detecting the presence of magnetized particles bonded to biological molecules that are affixed to a substrate. The adverse effect of hysteresis on the maintenance of a stable bias point for the magnetic moment of the sensor free layer is eliminated by a combination of biasing the sensor along its longitudinal direction rather than the usual transverse direction and by using the overcoat stress and magnetostriction of magnetic layers to create a compensatory transverse magnetic anisotropy. By making the spaces between the stripes narrower than the dimension of the magnetized particle and by making the width of the stripes equal to the dimension of the particle, the sensitivity of the sensor array is enhanced.

摘要翻译： 包括并联GMR传感器条的串联连接的传感器阵列提供了用于检测粘附到固定到基底上的生物分子的磁化颗粒的存在的敏感机制。 通过将传感器沿着其纵向方向而不是通常的横向偏置并通过使用传感器的外涂层应力和磁致伸缩的组合来消除滞后对维持传感器自由层的磁矩的稳定偏置点的不利影响 磁性层产生补偿横向磁各向异性。 通过使条纹之间的空间比磁化粒子的尺寸窄，并且通过使条纹的宽度等于粒子的尺寸，传感器阵列的灵敏度增强。

公开(公告)号：US20120135273A1

公开(公告)日：2012-05-31

申请号：US12927939

申请日：2010-11-30

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Guenole Jan

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Guenole Jan

IPC分类号： G11B5/706 ,  B05D5/00 ,  C23C14/34

CPC分类号： C23C14/3414 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3259 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12 ,  Y10T428/1114

摘要： A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20/NCC/Co10Fe70B20, Co10Fe70B20/NCC/Co10Fe70B20/NCC, or Co10Fe70B20/NCC/Co10Fe70B20/NCC/Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk⊥(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.

摘要翻译： 公开了具有通过自然氧化工艺形成的MgO隧道势垒的STT-RAM MTJ。 使用NCO是由Fe（20％） - SiO 2制成的纳米电流通道层的Co10Fe70B20 / NCC / Co10Fe70B20，Co10Fe70B20 / NCC / Co10Fe70B20 / NCC或Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20自由层配置，以使Jc0最小化 实现满足64Mb设计要求的更高的热稳定性，写电压，读电压，Ho和Hc值。 NCC层的厚度约为10埃，以符合最小Fe（Si）晶粒直径尺寸。 MTJ在约330℃的温度下退火，以保持高的磁阻比，同时使自由层的Hk⊥（界面）最大化，从而降低Heff并降低开关电流。 Co10Fe70B20层用低压工艺溅射沉积，功率约为15瓦，Ar流速为40标准立方厘米每分钟，以降低自由层的Heff。

公开(公告)号：US08058871B2

公开(公告)日：2011-11-15

申请号：US12217629

申请日：2008-07-08

申请人： Yimin Guo ,  Grace Gorman

发明人： Yimin Guo ,  Grace Gorman

IPC分类号： G01R33/02

CPC分类号： G01R33/098 ,  G01R15/205 ,  Y10T29/49075

摘要： Presented herein is a shunted MTJ sensor formed of a plurality of electrically connected MTJ cells for measuring magnetic fields and currents and its method of fabrication. To provide stable single domain magnetic moments of the MTJ cells and to ensure that the magnetic moments return to a fixed bias point in the absence of external magnetic fields, the cells are formed of sufficiently small size and with elliptical cross-section of aspect ratio greater than 1.2. To eliminate the possibility of ESD damage to the cells, they are protected by a parallel shunt, formed as a trace of sufficiently high resistance that directs accumulated charges harmlessly to ground while bypassing the cells.

摘要翻译： 这里提出的是由用于测量磁场和电流的多个电连接的MTJ电池及其制造方法形成的分流MTJ传感器。 为了提供MTJ单元的稳定的单畴磁矩，并且确保在没有外部磁场的情况下磁矩返回到固定偏置点，单元由足够小的尺寸形成，并且纵横比的椭圆截面更大 超过1.2。 为了消除对电池的ESD损伤的可能性，它们被并联分流器保护，形成为足够高的电阻痕迹，其在旁路电池时将累积的电荷无害地引导到地面。

公开(公告)号：US08057925B2

公开(公告)日：2011-11-15

申请号：US12079445

申请日：2008-03-27

申请人： Cheng T. Horng ,  Ru-Ying Tong

发明人： Cheng T. Horng ,  Ru-Ying Tong

IPC分类号： G11B5/39

CPC分类号： G01R33/098 ,  G01R33/1284 ,  G11C11/161 ,  H01L43/08 ,  H01L43/10 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T428/1107 ,  Y10T428/1114 ,  Y10T428/1121 ,  Y10T428/1129 ,  Y10T428/1136 ,  Y10T428/1143

摘要： A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.

摘要翻译： 公开了在STT-RAM器件中实现高dR / R的同时使自旋迁移磁化开关电流（Jc）最小化的双自旋滤波器。 底部自旋阀具有通过自然氧化工艺形成的MgO隧道阻挡层，以实现低RA，CoFe / Ru / CoFeB-CoFe钉扎层和具有中等纳米通道（NCC）的CoFeB / FeSiO / CoFeB复合材料自由层， 层以最小化Jc0。 NCC层可以是其中导电M（Si）晶粒与相邻铁磁层磁耦合并且形成在氧化物，氮化物或氧氮化物绝缘体基体中的复合材料。 上自旋阀具有Cu间隔物以降低自由层阻尼常数。 使用360℃的高退火温度将MR比提高到100％以上。 基于具有类似的MgO隧道势垒和复合自由层的MTJ的准静态测量，预期小于1×106A / cm 2的Jc0。

公开(公告)号：US08018758B2

公开(公告)日：2011-09-13

申请号：US12459655

申请日：2009-07-06

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.

公开(公告)号：US07884433B2

公开(公告)日：2011-02-08

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20100258888A1

公开(公告)日：2010-10-14

申请号：US12803189

申请日：2010-06-21

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

IPC分类号： H01L29/82

CPC分类号： H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/10 ,  H01L43/12

摘要： An STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

摘要翻译： 利用转移自旋角动量作为改变自由层的磁矩方向的机构的STT-MTJ MRAM单元。 该器件包括形成在被钉扎层的Ar离子等离子体平滑表面上的IrMn钉扎层，SyAP钉扎层，自然氧化的结晶的MgO隧道势垒层，在一个实施例中，包含非晶态的自由层 Co60Fe20B20层。 分别在3和6埃的Fe的两个结晶层之间形成约20埃的厚度。 自由层的特征在于低吉尔伯特阻尼因子和对传导电子的非常强的偏振作用。 所得到的电池具有低临界电流，高dR / R，并且多个这样的电池将呈现电阻和钉扎层磁化角分散的低变化。

公开(公告)号：US07804706B2

公开(公告)日：2010-09-28

申请号：US12313117

申请日：2008-11-17

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao

IPC分类号： G11C11/00

CPC分类号： H01L27/222 ,  G03F1/36 ,  H01L27/0207 ,  H01L43/12 ,  Y10S977/935

摘要： A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.

摘要翻译： 公开了底部电极（BE）布局，其具有在多个器件块中重复的四个不同部分，并且用于对MRAM中的BE层进行图案化。 器件部分包括具有基本相同形状和尺寸的BE形状和虚拟BE形状并且覆盖基本部分的大部分。 在多个虚拟BE形状中存在通孔，其中每个通孔将在WL焊盘上对准。 第二接合焊盘部分包括具有多个通孔的不透明区域。 剩下的两部分涉及MRAM中的开放场地区。 第三部分具有多个具有第一区域尺寸的虚拟BE形状。 第四部分具有多个具有大于第一区域尺寸的第二区域尺寸的虚拟BE形状，以提供更底层的蚀刻停止层ILD层的更完整的BE覆盖。

公开(公告)号：US07760544B2

公开(公告)日：2010-07-20

申请号：US12462434

申请日：2009-08-04

申请人： Yimin Guo ,  Jeff Chien

发明人： Yimin Guo ,  Jeff Chien

IPC分类号： G11C11/00

CPC分类号： H01L27/226 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  Y10S977/935

摘要： A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When RMTJ1>RMTJ2, the bit cell has a “0” state, and when RMTJ1

公开(公告)号：US07755933B2

公开(公告)日：2010-07-13

申请号：US12462453

申请日：2009-08-04

申请人： Yimin Guo ,  Jeff Chien

发明人： Yimin Guo ,  Jeff Chien

IPC分类号： G11C11/00

CPC分类号： H01L27/226 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  Y10S977/935

摘要： A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When RMTJ1>RMTJ2, the bit cell has a “0” state, and when RMTJ1

摘要翻译： 描述了具有两个子单元的自旋转移MRAM，每个子单元在上CPP单元和下MTJ单元之间具有导电间隔。 每个位单元中的两个导电间隔物由被写入字线控制的晶体管链接。 每个位单元中的两个CPP单元具有不同的电阻状态，并且每个子单元中的MTJ单元和CPP单元具有不同的电阻状态。 由于由CPP自由层施加的大的去磁场，MTJ自由层响应于CPP自由层中的切换而旋转。 公开了一种改进的电路设计，其能够实现更快和更可靠的读取过程，因为该参考是同一位单元内的第二MTJ。 当RMTJ1> RMTJ2时，位单元具有“0”状态，当RMTJ1