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151.发明申请公开(公告)号：US20210224041A1
公开(公告)日：2021-07-22
申请号：US16807194
申请日：2020-03-03
发明人： Po-Hao TSENG , Ming-Hsiu LEE , Yu-Hsuan LIN
摘要： A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.
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公开(公告)号：US20210200258A1
公开(公告)日：2021-07-01
申请号：US16080464
申请日：2017-09-28
申请人： Apple Inc.
发明人： Sharon Malevsky , Tomer Gidoni , Shahar Porat , Ayal Eshkoli , Tom Romano , Johannes Brendel , Stefan Meyer
摘要： Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.
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153.发明授权公开(公告)号：US11048650B1
公开(公告)日：2021-06-29
申请号：US16894899
申请日：2020-06-08
摘要： A method for integrating a processing-in-sensor unit and an in-memory computing includes the following steps. A providing step is performed to transmit the first command signal and the initial data to the in-memory computing unit. A converting step is performed to drive the first command signal and the initial data to convert to a second command signal and a plurality of input data through a synchronizing module. A fetching step is performed to drive a frame difference module to receive the input data to fetch a plurality of difference data. A slicing step is performed to drive a bit-slicing module to receive the difference data and slice each of the difference data into a plurality of bit slices. A controlling step is performed to encode the difference address into a control signal, and the in-memory computing unit accesses each of the bit slices according to the control signal.
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公开(公告)号：US20210193198A1
公开(公告)日：2021-06-24
申请号：US16951705
申请日：2020-11-18
发明人： James Brian Johnson
摘要： Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.
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公开(公告)号：US20210191453A1
公开(公告)日：2021-06-24
申请号：US16736819
申请日：2020-01-08
发明人： Sheng-Wen Chen , Shih-Yang Sun , Zhen-Hong Hung
IPC分类号： G06F1/10 , G06F1/08 , G06F1/12 , G11C11/4076 , G11C11/4074 , H03L7/08
摘要： A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
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公开(公告)号：US20210191452A1
公开(公告)日：2021-06-24
申请号：US16723273
申请日：2019-12-20
申请人： Arm Limited
摘要： A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*σmax; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.
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公开(公告)号：US11043946B1
公开(公告)日：2021-06-22
申请号：US16776776
申请日：2020-01-30
IPC分类号： H03K19/003 , G06F1/10 , H03K5/00
摘要： A method for adjusting a skew between a second clock signal and a first clock signal is provided. The second clock signal has been propagated from a first clock source through a second clock tree. The second clock tree comprises a programmable delay line that induces a delay. The method comprises at least one iteration of: measuring a skew between the second clock signal and the first clock signal, comparing an absolute difference of the measured skew and a sum of delay changes initiated in a time window preceding the measurement with a target skew, and initiating a delay change of the delay induced by the programmable delay line in the second clock tree depending on a result of the comparison.
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公开(公告)号：US20210181832A1
公开(公告)日：2021-06-17
申请号：US17247649
申请日：2020-12-18
申请人： Intel Corporation
发明人： Nausheen Ansari , Ziv Kabiry , Gal Yedidia
IPC分类号： G06F1/3296 , G06F3/14 , G06F1/10
摘要： In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.
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公开(公告)号：US20210181783A1
公开(公告)日：2021-06-17
申请号：US17112853
申请日：2020-12-04
发明人： Giuseppe Cavallaro
摘要： An embodiment electronic system comprises a first device, a second device and a clock generator circuit. The clock generator circuit is configured to provide a clock signal having a selectable frequency. The first device comprises a first processing circuit having coupled therewith a first Ethernet interface, and the second electronic device comprises a second processing circuit having coupled therewith a second Ethernet interface. At least one of the first device and the second device is configured to determine a frequency of the clock signal as a function of an operating parameter of the first device and/or of the second device and/or as a function of a parameter of the frames exchanged between the first device and the second device, and to act on the clock generator circuit to operate the clock generator circuit at the frequency.
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公开(公告)号：US20210173428A1
公开(公告)日：2021-06-10
申请号：US16315924
申请日：2019-01-04
发明人： Yong LIU , Yueqiang CHENG , Jian OUYANG , Tao WEI
摘要： According to one embodiment, a DP accelerator includes one or more execution units (EUs) configured to perform data processing operations in response to an instruction received from a host system coupled over a bus. The DP accelerator includes a security unit (SU) configured to establish and maintain a secure channel with the host system to exchange commands and data associated with the data processing operations. The DP accelerator includes a time unit (TU) coupled to the security unit to provide timestamp services to the security unit, where the time unit includes a clock generator to generate clock signals locally without having to derive the clock signals from an external source. The TU includes a timestamp generator coupled to the clock generator to generate a timestamp based on the clock signals, and a power supply to provide power to the clock generator and the timestamp generator.
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