公开(公告)号：US20040022211A1

公开(公告)日：2004-02-05

申请号：US10606189

申请日：2003-06-25

Applicant: STMicroelectronics N.V.

Inventor： Patrick Conti

IPC: H04B007/00

CPC classification number: H04B1/006 ,  H04B1/005 ,  H04B1/406 ,  H04B1/48

Abstract: A radio-frequency switching device includes first and second radio-frequency channels connected to an input/output terminal. A controllable switching device selects one of the radio-frequency channels in response to a switching control signal. The switching device includes a respective control module connected to each radio-frequency channel. Each control module includes a PIN diode whose cathode is connected to the input/output terminal, and a control transistor whose base is connected to a control input for receiving the switching control signal. A conducting terminal of the control transistor is connected to the anode of the PIN diode.

Abstract translation: 射频切换装置包括连接到输入/输出终端的第一和第二射频信道。 可控切换装置响应于切换控制信号选择射频信道之一。 交换设备包括连接到每个射频信道的相应控制模块。 每个控制模块包括PIN二极管，其阴极连接到输入/输出端子，以及控制晶体管，其基极连接到用于接收开关控制信号的控制输入端。 控制晶体管的导电端子连接到PIN二极管的阳极。

公开(公告)号：US20030060167A1

公开(公告)日：2003-03-27

申请号：US10253769

申请日：2002-09-24

Applicant: STMicroelectronics N.V.

Inventor： Corinne Bonhomme

IPC: H04B017/00

CPC classification number: H04L25/0204 ,  H04B1/71057

Abstract: First estimations of the fading coefficients of a multi-path transmission channel are carried out in the sense of maximum likelihood. Sets of Wiener filter coefficients are stored according to predetermined speeds of movement of the mobile terminal and predetermined power levels of the signal. The real speed of the mobile terminal is estimated and the power of the signal for each path is measured. From this, a set of Wiener filter coefficients is derived with which the first estimations are filtered to obtain the final estimation of the fading coefficients.

Abstract translation: 在多径传输信道的衰落系数的第一估计是在最大似然的意义上进行的。 维纳滤波器系数的集合根据移动终端的预定移动速度和信号的预定功率电平来存储。 估计移动终端的实际速度，并测量每个路径的信号功率。 从此，导出一组维纳滤波器系数，利用该组合对第一估计进行滤波以获得衰落系数的最终估计。

公开(公告)号：US20020145551A1

公开(公告)日：2002-10-10

申请号：US10113837

申请日：2002-04-01

Applicant: STMicroelectronics N.V.

Inventor： Thierry Arnaud ,  Friedbert Berens

IPC: H03M003/00

CPC classification number: H03M3/392 ,  H03M3/458

Abstract: A remote terminal includes a receiver stage for receiving a transmitted signal and for delivering an analog signal. The remote terminal further includes an analog/digital converter for converting the analog signal to a digital signal, and a processing stage for processing the digital signal. The analog/digital converter is a delta-sigma converter having adjustable parameters, and the processing stage includes a tuning circuit for adjusting these parameters on the fly as a function of the transmission standard, of the actual rate of transmission of the useful data, and of the actual conditions of reception.

Abstract translation: 远程终端包括用于接收发射信号和传送模拟信号的接收机级。 远程终端还包括用于将模拟信号转换为数字信号的模拟/数字转换器，以及用于处理数字信号的处理级。 模拟/数字转换器是具有可调整参数的Δ-Σ转换器，并且处理级包括用于根据传输标准即时调整这些参数的调整电路，用于有用数据的实际传输速率，以及 的实际接待条件。

公开(公告)号：US20020012384A1

公开(公告)日：2002-01-31

申请号：US09907086

申请日：2001-07-17

Applicant: STMicroelectronics N.V.

Inventor： Friedbert Berens

IPC: H04K001/00

CPC classification number: H04B1/7115 ,  H04B1/7117

Abstract: A rake receiver uses a delayed version of the received sequence and a delayed version of a scrambling code. The flexible hardware structure of the time-aligning and descrambling unit includes at least two delay chains and one multiplier. By controlling two multiplexers, the delayed versions of the received sequence can be multiplied with an arbitrary scrambling code having an arbitrary phase. During one chip period, one multiplication is performed for each path to be processed.

Abstract translation: 瑞克接收机使用接收到的序列的延迟版本和扰码的延迟版本。 时间对准和解扰单元的灵活的硬件结构包括至少两个延迟链和一个乘法器。 通过控制两个多路复用器，接收序列的延迟版本可以与具有任意相位的任意扰码相乘。 在一个码片周期期间，对每个待处理的路径执行一次乘法。

公开(公告)号：US20020010010A1

公开(公告)日：2002-01-24

申请号：US09886966

申请日：2001-06-21

Applicant: STMicroelectronics N.V.

Inventor： Thierry Arnaud ,  Friedbert Berens

IPC: H04M001/00

CPC classification number: H04W52/029 ,  H03J7/065 ,  Y02D70/1242

Abstract: The electrical consumption of a cellular mobile telephone is reduced by using fractional-division phase-locked loops receiving a frequency reference from a fairly inaccurate quartz oscillator. Electrical consumption is also reduced by switching the output of the oscillator onto the input of the processing stage when the transmission/reception stage is inactive. The fractional-division phase-locked loops can then be deactivated.

Abstract translation: 通过使用从相当不准确的石英振荡器接收频率参考的分数分频锁相环来减少蜂窝移动电话的电力消耗。 当发送/接收阶段不活动时，通过将振荡器的输出切换到处理级的输入端也可以减少电力消耗。 然后可以停用分数分频锁相环。

公开(公告)号：US6098185A

公开(公告)日：2000-08-01

申请号：US961841

申请日：1997-10-31

Applicant: Aaron W. Wilson

Inventor： Aaron W. Wilson

IPC: G11B5/012 ,  G11B20/18 ,  G11B27/30 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11B20/1883 ,  G11B27/3027 ,  G11B2220/20 ,  G11B5/012

Abstract: A method and data structure for a header-formatted defective sector management system. A spare sector is allocated for each n sectors. When a defective one of the n sectors is identified, the sectors are slipped using the spare sector. The location of the defective sector and the type of defect, e.g., data field or header field, is indicated by a data structure written to the header field of at least one of the non-defective sectors. When a second defective sector is identified, the system operates to disposition the second defective sector based on the type of the first defective sector. If the first defective sector was a defect in the data field and the second defective sector is a defect in the header field then the first defective sector is converted to a reassigned sector and the second defective sector is slipped. This avoids the problem of reassigning a sector having a defective header field.

Abstract translation: 标题格式的缺陷扇区管理系统的方法和数据结构。 为每个n个扇区分配备用扇区。 当识别出n个扇区中的有缺陷的扇区时，扇区使用备用扇区滑动。 缺陷扇区的位置和缺陷的类型，例如数据字段或报头字段由写入至少一个无缺陷扇区的报头字段的数据结构指示。 当识别到第二缺陷扇区时，系统基于第一缺陷扇区的类型来操作以配置第二缺陷扇区。 如果第一缺陷扇区是数据场中的缺陷，并且第二缺陷扇区是报头字段中的缺陷，则第一缺陷扇区被转换为重新分配的扇区，并且第二缺陷扇区被滑动。 这避免了重新分配具有缺陷头字段的扇区的问题。

公开(公告)号：US6072650A

公开(公告)日：2000-06-06

申请号：US939063

申请日：1997-09-29

Applicant: Aaron Wade Wilson

Inventor： Aaron Wade Wilson

IPC: G11B5/012 ,  G11B19/04 ,  G11B20/12 ,  G11B27/30 ,  G11B5/09

CPC classification number: G11B20/1252 ,  G11B19/04 ,  G11B27/30 ,  G11B2020/1232 ,  G11B2220/2516 ,  G11B5/012

Abstract: The invention comprises a magnetic disk storage system and comprises method for configuring the magnetic disk storage system. The magnetic disk storage system facilitates write and read operations that compensate for variances that are experienced with magnetic disk storage systems. When writing data to a data sector, the magnetic disk storage system utilizes a phase lock oscillator field that has a length that is specified for that data sector. When reading from a data sector, the magnetic disk storage system utilizes an incremental read delay that has a duration that is specified for that data sector. Data sectors with shorter data sector delay periods can have shorter phase lock oscillator fields than data sectors with larger data sector delay periods. This frees-up memory space and increases the capacity and performance of the magnetic disk storage system.

Abstract translation: 本发明包括磁盘存储系统，并且包括用于配置磁盘存储系统的方法。 磁盘存储系统便于写入和读取操作，以补偿磁盘存储系统遇到的差异。 当将数据写入数据扇区时，磁盘存储系统利用了具有为该数据扇区指定的长度的锁相振荡器字段。 当从数据扇区读取时，磁盘存储系统利用具有为该数据扇区指定的持续时间的增量读延迟。 具有较短数据扇区延迟周期的数据扇区可以具有比具有较大数据扇区延迟周期的数据扇区更短的锁相振荡器场。 这释放了内存空间，并增加了磁盘存储系统的容量和性能。

公开(公告)号：US6064634A

公开(公告)日：2000-05-16

申请号：US914296

申请日：1997-08-18

Applicant: John S. Packer

Inventor： John S. Packer

IPC: G11B19/12 ,  G11B27/00 ,  G11B27/30 ,  G11B27/32 ,  G11B17/22

CPC classification number: G11B19/12 ,  G11B27/005 ,  G11B27/3063 ,  G11B27/329 ,  G11B2220/2545

Abstract: Disclosed is a compact disc apparatus having automatic start capabilities. The compact disc apparatus includes a digital signal processor for reading sectors that have a plurality of EFM frames, and the EFM frames contain at least a data component and a subcode component. Also included is a Q-subcode extractor for retrieving a Q-bit from each of the plurality of EFM frames being read by the digital signal processor. An auto-start unit is further included to analyze and process the retrieved Q-bits from each of the plurality of EFM frames, such that a determination is made as to whether a minute/second/frame derived from the retrieved Q-bits matches a desired start minute/second/frame location. Wherein the data being read from sectors by the digital signal processor starts transferring data to a memory beginning with the desired start minute/second/frame when the match is found by the auto-start unit.

Abstract translation: 公开了一种具有自动启动能力的光盘装置。 光盘装置包括用于读取具有多个EFM帧的扇区的数字信号处理器，并且EFM帧至少包含数据组件和子代码组件。 还包括一个Q子代码提取器，用于从由数字信号处理器读取的多个EFM帧中的每一个中检索Q位。 进一步包括自动启动单元以分析和处理从多个EFM帧中的每一个获得的Q位，使得确定从所检索的Q位导出的分/秒/帧是否匹配 期望开始分钟/秒/帧位置。 其中，当由自动启动单元找到匹配时，由数字信号处理器从扇区读取的数据开始以期望的开始分/秒/帧开始传送到存储器。

公开(公告)号：US6054828A

公开(公告)日：2000-04-25

申请号：US216623

申请日：1998-12-16

Applicant: John P. Hill

Inventor： John P. Hill

IPC: G11B5/596 ,  G11B21/08 ,  H03M1/66 ,  G05B11/01 ,  G05B13/00 ,  G11B7/00

CPC classification number: G11B21/085 ,  H03M1/66 ,  G11B5/59622

Abstract: Disclosed is a tracking control integrated circuit (IC) system implementation and method for controlling the gain of a digital-to-analog converter in a disk drive system. The tracking control IC system includes components defined in integrated circuit chips and components defined on a printed circuit board. The tracking control IC system is configured to be implemented in a disk drive system that includes a disk media. The tracking control IC system includes a servo controller chip that includes a compensator/processor, the digital-to-analog converter, and a switch. The switch is configured to receive a high gain signal (being Low or High) for setting the switch in an open state or a closed state. The tracking control IC system further includes a power amplifier chip having amplifying elements. The power amplifier chip has a first input and a second input, both of which connect to selected ones of the amplifying elements. The digital-to-analog converter includes a first output that is in communication with the switch and the first input of the power amplifier chip. The digital-to-analog converter has a second output that is in communication with the switch, and the switch has an output that is coupled to the first input of the power amplifier chip through the selected amplifying elements. The switch therefore enables the tracking control IC system to have a wider dynamic range control voltage Vc without increasing the die area of the servo control chip, without adding external active components to the PCB, and without increasing the control signal's susceptibility to noise pickup or offsets.

Abstract translation: 公开了一种用于控制磁盘驱动器系统中的数模转换器的增益的跟踪控制集成电路（IC）系统实现和方法。 跟踪控制IC系统包括在印刷电路板上限定的集成电路芯片和部件中定义的组件。 跟踪控制IC系统被配置为在包括盘介质的磁盘驱动器系统中实现。 跟踪控制IC系统包括包括补偿器/处理器，数模转换器和开关的伺服控制器芯片。 开关被配置为接收高增益信号（低或高），用于将开关置于打开状态或关闭状态。 跟踪控制IC系统还包括具有放大元件的功率放大器芯片。 功率放大器芯片具有第一输入和第二输入，两者均连接到选定的放大元件。 数模转换器包括与开关和功率放大器芯片的第一输入通信的第一输出。 数模转换器具有与开关通信的第二输出，并且开关具有通过所选择的放大元件耦合到功率放大器芯片的第一输入的输出。 因此，该开关能够使跟踪控制IC系统具有更宽的动态范围控制电压Vc，而不增加伺服控制芯片的管芯面积，而不会增加外部有源元件到PCB，并且不增加控制信号对噪声拾取或偏移的敏感性 。

公开(公告)号：US09325488B2

公开(公告)日：2016-04-26

申请号：US14817996

申请日：2015-08-04

Applicant: STMicroelectronics N.V.

Inventor： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC: H04L7/00 ,  H03H17/06 ,  H04L7/02

CPC classification number: H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

Abstract: An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract translation: 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。