公开(公告)号：US07960778B2

公开(公告)日：2011-06-14

申请号：US12314163

申请日：2008-12-05

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/792

Abstract: The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.

Abstract translation: 本发明涉及闪存单元串。 闪存单元串包括连接到单元设备的端部的多个单元设备和交换设备。 每个电池器件包括依次形成在半导体衬底上的半导体衬底和透射绝缘层，电荷存储节点，控制绝缘层和控制电极。 在闪速存储单元串中，在单元装置与相邻单元装置之间的半导体基板上设置掩埋绝缘层，能够容易地形成执行源/漏功能的反转层。 根据本发明，NAND闪存的单元装置的还原特性和性能得到改善，如果需要，通过来自控制电极和电荷存储节点的边缘电场来感应通道的反转层。

公开(公告)号：US20100270619A1

公开(公告)日：2010-10-28

申请号：US12310532

申请日：2007-08-27

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the fence-shaped body; a gate insulating layer formed at side walls and an upper surface of the fence-shaped body at which the insulating layer is not formed; a gate electrode formed on the gate insulating layer; source/drain formed at regions of the fence-shaped body where the gate electrode is not formed. The gate electrode includes first and second gate electrodes which are in contact with each other and have different work functions. Particularly, the second gate electrode having a low work function is disposed to be close to the drain. As a result, the FinFET according to the present invention increases a threshold voltage by using a material having the high work function for the gate electrode and lowers the work function of the gate electrode overlapping with the drain, so that gate induced drain leakage (GIDL) can be reduced.

Abstract translation: 提供了具有低漏电流的鳍式场效应晶体管（FinFET）及其制造方法。 FinFET包括：体硅衬底; 通过图案化基板形成的栅栏体; 在所述基板的表面上形成到所述栅栏状体的第一高度的绝缘层; 在侧壁形成的栅极绝缘层和不形成绝缘层的栅栏状体的上表面; 形成在所述栅极绝缘层上的栅电极; 源极/漏极形成在栅极体的不形成栅电极的区域处。 栅电极包括彼此接触并具有不同功函数的第一和第二栅电极。 特别地，具有低功函数的第二栅电极设置成靠近漏极。 结果，根据本发明的FinFET通过使用具有用于栅电极的高功函数的材料来增加阈值电压，并降低与漏极​​重叠的栅电极的功函数，从而导致漏极漏极（GIDL ）可以减少。

公开(公告)号：US20100219929A1

公开(公告)日：2010-09-02

申请号：US12738016

申请日：2008-10-14

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01H85/02

CPC classification number: H01H37/765

Abstract: Disclosed is a thermal fuse structured in such a manner that a resistance heating element which generates heat according to an electric current is mounted within a case charged with a solid fusible material so that the fusible material is liquefied by heat of the resistance heating element caused by the external temperature and also by the current applied to a circuit, accordingly disconnecting the circuit. Since the resistance heating element is integrally formed in the case, the thermal fuse is capable of functioning as both a thermal fuse and a current fuse, disconnecting the circuit by both the external heat and the overcurrent. Especially, when the resistance heating element comprises a positive thermal coefficient (PTC) element capable of temperature measurement, the current flowing through the circuit can be measured.

Abstract translation: 公开了一种热熔丝，其结构使得根据电流产生热量的电阻加热元件安装在装有固体可熔材料的壳体内，使得易熔材料由于电阻加热元件的热​​量而液化，由 外部温度以及施加到电路的电流，从而断开电路。 由于电阻加热元件在壳体中整体形成，所以热熔丝能够用作热熔丝和电流保险丝，同时通过外部热和过电流来断开电路。 特别地，当电阻加热元件包括能够进行温度测量的正热系数（PTC）元件时，可以测量流过电路的电流。

公开(公告)号：US20100210061A1

公开(公告)日：2010-08-19

申请号：US12605162

申请日：2009-10-23

Applicant: Chaehwan Jeong ,  Jong Ho Lee ,  Ho-Sung Kim ,  Seongjae Boo

Inventor： Chaehwan Jeong ,  Jong Ho Lee ,  Ho-Sung Kim ,  Seongjae Boo

IPC: H01L31/18

CPC classification number: H01L21/02381 ,  C23C16/24 ,  C23C16/507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02592 ,  H01L21/0262 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/03921 ,  H01L31/075 ,  H01L31/077 ,  H01L31/1824 ,  H01L31/202 ,  H01L31/204 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

Abstract: A method for fabricating a solar cell using inductively coupled plasma chemical vapor deposition (ICP-CVD) including a first electrode, a P layer, an intrinsic layer, an N-type layer and a second electrode. The method includes forming an intrinsic layer including a hydrogenated amorphous silicon (Si) thin film by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas and silane (SiH4) gas. In the mixed gas, silane gas is in a ratio of 8 to 10 relative to mixed gas.

Abstract translation: 一种使用包括第一电极，P层，本征层，N型层和第二电极的电感耦合等离子体化学气相沉积（ICP-CVD）制造太阳能电池的方法。 该方法包括通过使用包含氢（H 2）气和硅烷（SiH 4）气体的混合气体的电感耦合等离子体化学气相沉积（ICP-CVD）装置形成包括氢化非晶硅（Si）薄膜的本征层。 在混合气体中，相对于混合气体，硅烷气体的比率为8〜10。

公开(公告)号：US20100207180A1

公开(公告)日：2010-08-19

申请号：US12708342

申请日：2010-02-18

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: H01L27/108

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.

Abstract translation: 提供了一种包括衬底的单晶体管（1T）浮体DRAM单元器件; 形成在基板上的栅极堆叠; 控制电极，其设置在所述基板上，并且其一些或全部部分被所述栅极堆叠包围; 形成在栅叠层上的半导体层; 源极和漏极，其形成在半导体层的表面中并且其下表面不与栅极堆叠接触; 形成在半导体层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅极，其中，除了所述源极和漏极之外的所述半导体层的剩余部分被构造为浮体。 可以提高基于MOS的DRAM单元装置的小型化特性和性能，并且可以提高存储容量。

公开(公告)号：US07767512B2

公开(公告)日：2010-08-03

申请号：US12019449

申请日：2008-01-24

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

Abstract translation: 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US20100163947A1

公开(公告)日：2010-07-01

申请号：US12632115

申请日：2009-12-07

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/40

Abstract: A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed.

Abstract translation: 一种PIP电容器及其方法。 制造PIP电容器的方法可以包括在硅衬底上形成场氧化物膜以限定器件隔离区和/或有源区。 制造PIP电容器的方法可以包括在场氧化物膜上形成具有掺杂杂质的下部多晶硅电极。 制造PIP电容器的方法可以包括执行氧化步骤以在活性区上和/或上方在多晶硅和/或第二氧化物膜上形成第一氧化膜。 制造PIP电容器的方法可以包括在第一氧化物膜的区域上和/或上方形成上部多晶硅电极，并且在基本上同时在第二氧化膜上形成和/或在第二氧化物膜上形成栅电极。 制造PIP电容器的方法可以包括形成多晶硅电阻器。 公开了一种PIP电容器。

公开(公告)号：US20100102372A1

公开(公告)日：2010-04-29

申请号：US12200929

申请日：2008-08-28

Applicant: Jong-Ho Lee ,  Ki-Heung Park

Inventor： Jong-Ho Lee ,  Ki-Heung Park

IPC: H01L27/108 ,  H01L21/84

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.

Abstract translation: 提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。 单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。 在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。

公开(公告)号：US20100092832A1

公开(公告)日：2010-04-15

申请号：US12539353

申请日：2009-08-11

Applicant: Hae-Weon LEE ,  Jong Ho Lee ,  Eun Oak Oh ,  Ji-Won Son ,  Hae-Ryoung Kim ,  Hyoungchul Kim ,  Kyung-ryul Lee

Inventor： Hae-Weon LEE ,  Jong Ho Lee ,  Eun Oak Oh ,  Ji-Won Son ,  Hae-Ryoung Kim ,  Hyoungchul Kim ,  Kyung-ryul Lee

IPC: H01M8/10 ,  B05D5/12 ,  B05D1/04 ,  C09D1/00

CPC classification number: H01M8/1253 ,  C09D1/00 ,  H01M2008/1293 ,  Y02E60/525 ,  Y02P70/56

Abstract: A metal oxide thin film structure for a solid oxide fuel cell, prepared by a method comprising dispersing a metal oxide nanopowder in a metal oxide salt solution and subsequent coating of the resulting metal oxide powder dispersed sol and the metal oxide salt solution on a porous substrate, has excellent gas impermeability, excellent phase stability, and is devoid of cracks or pinholes.

Abstract translation: 一种用于固体氧化物燃料电池的金属氧化物薄膜结构，其通过包括将金属氧化物纳米粉末分散在金属氧化物盐溶液中并随后将所得金属氧化物粉末分散溶胶和金属氧化物盐溶液涂覆在多孔基材上的方法制备 具有优异的气体不透性，优异的相稳定性，没有裂纹或针孔。

公开(公告)号：US20100013021A1

公开(公告)日：2010-01-21

申请号：US12176634

申请日：2008-07-21

Applicant: Xiangdong Chen ,  Jong Ho Lee ,  Weipeng Li ,  Dae-Gyu Park ,  Kenneth J. Stein ,  Voon-Yew Thean

Inventor： Xiangdong Chen ,  Jong Ho Lee ,  Weipeng Li ,  Dae-Gyu Park ,  Kenneth J. Stein ,  Voon-Yew Thean

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/2652 ,  H01L21/823807 ,  H01L29/1054

Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).

Abstract translation: 公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件 其包括PFET和形成PFET单独和CMOS器件的方法。 实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。