公开(公告)号：US20060047036A1

公开(公告)日：2006-03-02

申请号：US10929239

申请日：2004-08-30

Applicant: Jun Lin

Inventor： Jun Lin

IPC: C08K5/24

CPC classification number: C08G18/792 ,  C08G18/2825 ,  C09D175/04 ,  C09D201/025 ,  C09D201/10 ,  C08L2666/16

Abstract: A curable film-forming coating composition, typically a clearcoat, having improved compatibility over waterborne and solventborne basecoats. The composition includes a film-forming binder comprising a carbamate material, a curing agent, typically a monomeric melamine curing agent, and a hydroxy functional silane component. When used as a clearcoat over a standard pigmented basecoat, the resulting coating provides a substantially wrinkle free appearance and excellent adhesion to both waterborne and solventborne basecoats.

Abstract translation: 一种可固化的成膜涂料组合物，通常为透明涂料，具有改善的相对于水性和溶剂型底涂层的相容性。 组合物包括含有氨基甲酸酯材料，固化剂，通常为单体三聚氰胺固化剂和羟基官能的硅烷组分的成膜粘合剂。 当用作标准着色底漆时的透明涂层时，所得涂层提供基本上无皱纹的外观和对水性和溶剂型底涂层的优异粘合性。

公开(公告)号：US06942320B2

公开(公告)日：2005-09-13

申请号：US10057025

申请日：2002-01-24

Applicant: Chen-Kuei Chung ,  Chun-Jun Lin ,  Chung-Chu Chen

Inventor： Chen-Kuei Chung ,  Chun-Jun Lin ,  Chung-Chu Chen

IPC: B41J2/14 ,  B41J2/16 ,  B41J2/05

CPC classification number: B41J2/1645 ,  B41J2/14129 ,  B41J2/14145 ,  B41J2/1603 ,  B41J2/1625 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1642 ,  B41J2/1643 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49151 ,  Y10T29/49153 ,  Y10T29/49401

Abstract: A method for fabricating a thermal inkjet head equipped with a symmetrical heater and the head fabricated by the method are provided. The method incorporates two thick photoresist deposition processes and a nickel electroplating process. The first thick photoresist deposition process is carried out to form an ink chamber in fluid communication with a funnel-shaped manifold and an injector orifice. The second thick photoresist deposition process forms a mold for forming an injector passageway that leads to the injector orifice. The nickel electroplating process provides an orifice plate on top of the inkjet head through which an injector passageway that leads to the injector orifice is provided for injecting ink droplets.

Abstract translation: 提供一种制造配备有对称加热器的热喷墨头和通过该方法制造的头的方法。 该方法包括两个厚的光致抗蚀剂沉积工艺和镍电镀工艺。 进行第一厚的光致抗蚀剂沉积工艺以形成与漏斗形歧管和喷射器孔流体连通的墨室。 第二厚的光致抗蚀剂沉积工艺形成用于形成通向喷射孔的喷射器通道的模具。 镍电镀工艺在喷墨头的顶部提供孔板，通过该孔板提供通向喷射器孔口的喷射器通道用于喷射墨滴。

公开(公告)号：US06924193B2

公开(公告)日：2005-08-02

申请号：US10705889

申请日：2003-11-13

Applicant: Jun Lin ,  Chung-Ming Chu ,  Toshiya Suzuki ,  Katsuhiko Hieda

Inventor： Jun Lin ,  Chung-Ming Chu ,  Toshiya Suzuki ,  Katsuhiko Hieda

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/91

Abstract: A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.

Abstract translation: 制造电容器的方法包括以下步骤：在衬底上形成金属的下电极; 在下电极上形成氧化物电介质膜的电容器电介质膜; 在电容器电介质膜上沉积金属膜; 在沉积金属膜的步骤之后在氢含量气氛中进行热处理; 以及在进行热处理的步骤之后图案化金属膜以形成金属膜的上电极。 因此，改善了上电极和电容器电介质膜之间的粘附性，并且可以提高电容器特性。

公开(公告)号：US06818936B2

公开(公告)日：2004-11-16

申请号：US10288197

申请日：2002-11-05

Applicant: Chrong Jun Lin ,  Hsin-Ming Chen

Inventor： Chrong Jun Lin ,  Hsin-Ming Chen

IPC: H01L27108

CPC classification number: H01L28/40 ,  H01L21/28273 ,  H01L28/91 ,  H01L29/42324 ,  H01L29/66825

Abstract: A single-poly EEPROM cell is disclosed with a vertically formed metal-insulator-metal (MIM) coupling capacitor, which serves as a control gate in place of a laterally buried control gate thereby eliminating the problem of junction breakdown, and at the same time reducing the size of the cell substantially. A method of forming the single-poly cell is also disclosed. This is accomplished by forming a floating gate over a substrate with an intervening tunnel oxide and then the MIM capacitor over the floating gate with another intervening dielectric layer between the top metal and the lower metal of the capacitor where the latter metal is connected to the polysilicon floating gate.

Abstract translation: 公开了具有垂直形成的金属 - 绝缘体 - 金属（MIM）耦合电容器的单聚电解质电池单元，其用作控制栅极以代替横向埋设的控制栅极，从而消除了结击穿的问题，并且同时 基本上减小了细胞的大小。 还公开了形成单多晶硅电池的方法。 这是通过在衬底上形成具有中间隧道氧化物的浮动栅极，然后在浮动栅极上形成MIM电容器，在电容器的顶部金属和下部金属之间的另一个中间介电层，其中后者金属连接到多晶硅 浮动门。

公开(公告)号：US06803625B2

公开(公告)日：2004-10-12

申请号：US10627013

申请日：2003-07-25

Applicant: Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

Inventor： Chia-Ta Hsieh ,  Di Son Kuo ,  Chrong-Jun Lin ,  Wen-Ting Chu

IPC: H01L2978

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

公开(公告)号：US06242313B1

公开(公告)日：2001-06-05

申请号：US09389891

申请日：1999-09-03

Applicant: Jei-Feng Hwang ,  Jun-Lin Tsai ,  Ruey-Hsin Liou ,  Jyh-Min Jiang

Inventor： Jei-Feng Hwang ,  Jun-Lin Tsai ,  Ruey-Hsin Liou ,  Jyh-Min Jiang

IPC: H01L21331

CPC classification number: H01L29/404 ,  H01L21/765 ,  H01L21/8249 ,  H01L29/66272

Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates. The ability to increase collector —emitter breakdowns, via use of only polysilicon field plates, allows the use of higher N well dopant concentrations, thus resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated with the lower N well dopant concentrations, where the lower N well dopant concentration is needed to achieve the desired, increased collector emitter breakdowns.

Abstract translation: 已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列的特点是使用多晶硅场板。 放置在场氧化物区域中，其中场氧化物区域位于其间的P型，基极和N型集电极区域的N阱区域的区域中。 多晶硅场板的使用导致集电极 - 发射极击穿电压的增加，这是由于多晶硅场板下面的电场的电场减少的结果。 通过仅使用多晶硅场板来增加集电极 - 发射体击穿的能力允许使用更高的N阱掺杂剂浓度，从而导致BPCB器件的频率响应（Ft）增加，与使用 较低的N阱掺杂剂浓度，其中需要较低的N阱掺杂剂浓度以实现期望的增加的集电极发射极击穿。

公开(公告)号：US5757351A

公开(公告)日：1998-05-26

申请号：US570643

申请日：1995-12-11

Applicant: Jun Lin ,  Homer L. Webb ,  Linda S. Walling ,  Barry E. Young ,  J. Scott Denko

Inventor： Jun Lin ,  Homer L. Webb ,  Linda S. Walling ,  Barry E. Young ,  J. Scott Denko

IPC: G09G3/20 ,  G09G3/36

CPC classification number: G09G3/2085 ,  G09G3/3688 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G3/20

Abstract: The present invention uses temporary storage of data sub-frames to obviate the need for a multiplicity of driver circuit packages and eliminate the traditional one-to-one association of driver circuit channels with selected data electrodes in the addressing of a flat panel display matrix. Display data signals are serially induced along a controlled velocity signal propagation transmission line to create signal profiles representative of data sub-frames, a data frame being the amount of data required to address a single display row. Individual informational "bits" of the data sub-frame are captured, in timed sequence or in parallel, from the signal profile by the multiplexer assemblies tapped into the transmission line at particular sites along its length. When the assemblies are enabled, the signal profile along the transmission line is exposed to a charge storage capability. The informational bits of the signal profile representing the sub-frame are, consequently, captured. Sequential capturing and storage of data sub-frames continues until a complete data frame of matrix information has been stored. When the bits of plural sub-frames sufficient in total to address an entire row have been stored, the stored data frame is available on the column electrodes and a row select strobe signal closes an electrical path between the multiple data sub-frames available from the columns and a selected row thus recomposing the full data frame at the strobed row to display the data.

Abstract translation: 本发明使用数据子帧的临时存储来消除对多个驱动器电路封装的需要，并且消除了在平板显示矩阵的寻址中的所选数据电极的驱动器电路通道的传统一对一关联。 显示数据信号沿着受控速度信号传播传输线被串行地引导以产生表示数据子帧的信号轮廓，数据帧是寻址单个显示行所需的数据量。 数据子帧的单个信息“比特”按照定时顺序或并行地从信号分布被多路复用器组件沿着其长度在特定位置分接到传输线中被捕获。 当组件被使能时，沿着传输线的信号轮廓被暴露于电荷存储能力。 因此，捕获表示子帧的信号简档的信息比特。 数据子帧的顺序捕获和存储继续，直到已经存储了矩阵信息的完整数据帧。 当已经存储了总共足以寻址整行的多个子帧的位时，存储的数据帧在列电极上可用，并且行选择选通信号关闭可从该电路获得的多个数据子帧之间的电路径 列和所选择的行，从而重组在选通行处的完整数据帧以显示数据。