公开(公告)号：US08013063B2

公开(公告)日：2011-09-06

申请号：US10567000

申请日：2004-05-13

Applicant: Kwang-jin Lee ,  Jeong-heon Ahn ,  Hye-kyong Lee

Inventor： Kwang-jin Lee ,  Jeong-heon Ahn ,  Hye-kyong Lee

IPC: C08F30/08 ,  C08F30/00

CPC classification number: C08F265/00 ,  C08F265/04 ,  C08F265/06 ,  C08F265/10 ,  C08F285/00 ,  C08F291/00 ,  C08G77/442 ,  C08L27/06 ,  C08L51/00 ,  C08L51/003 ,  Y10S525/902 ,  C08F2/22 ,  C08L2666/24 ,  C08L2666/02

Abstract: The present invention relates to acryl-silicone hybrid impact modifiers, the method of their manufacture, and vinyl chloride resin compositions containing the above. The acryl-silicone hybrid impact modifier of the present invention contains a seed obtained through emulsion copolymerization of vinyl monomers and hydrophilic monomers; an acryl-silicone hybrid rubber core covering the seed in which a polyorganosiloxane rubber phase is dispersed locally onto the inner part and surface of the acrylic rubber core containing alkyl acrylate polymers and a shell covering the above rubber core and containing alkyl methacrylate polymers. Thermoplastic resins containing the above, particularly by being added to vinyl chloride resins, they have effects of granting superior impact resistance, weatherability, and high gloss.

Abstract translation: 本发明涉及丙烯酸 - 硅氧烷混合抗冲改性剂，其制造方法和含有上述的氯乙烯树脂组合物。 本发明的丙烯酸 - 硅氧烷杂化抗冲改性剂含有通过乙烯基单体和亲水性单体的乳液共聚获得的种子; 覆盖种子的丙烯酸 - 硅氧烷混合橡胶芯，其中聚有机硅氧烷橡胶相局部分散在丙烯酸酯橡胶芯的内部和表面上，该丙烯酸橡胶芯含有丙烯酸烷基酯聚合物和覆盖上述橡胶芯并且含有甲基丙烯酸烷基酯聚合物的壳。 含有上述的热塑性树脂，特别是通过加入到氯乙烯树脂中，它们具有赋予优异的耐冲击性，耐候性和高光泽度的效果。

公开(公告)号：US20110179237A1

公开(公告)日：2011-07-21

申请号：US13064476

申请日：2011-03-28

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Yong Jun Lee

IPC: G06F12/00

CPC classification number: G11C13/0061 ,  G11C7/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004

Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.

Abstract translation: 一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

公开(公告)号：US07978490B2

公开(公告)日：2011-07-12

申请号：US11892851

申请日：2007-08-28

Applicant: Kwang-jin Lee ,  Du-eung Kim

Inventor： Kwang-jin Lee ,  Du-eung Kim

IPC: G11C15/00

CPC classification number: G11C15/046 ,  G11C13/0004

Abstract: According to an example embodiment, a CAM cell included in a CAM may include a phase change memory device, a connector, and/or a developer. The phase change memory device may be configured to store data. The phase change memory device may have a resistance that may be varied according to the logic level of the stored data. The connector may be configured to control writing data to the phase change memory device and reading data from the phase change memory device. The developer may be configured to control reading data from the phase change memory device in a search mode in which the data stored in the phase change memory device is compared to the search data.

Abstract translation: 根据示例实施例，CAM中包括的CAM单元可以包括相变存储器件，连接器和/或显影器。 相变存储器件可以被配置为存储数据。 相变存储器件可以具有可以根据存储的数据的逻辑电平而改变的电阻。 连接器可以被配置为控制向相变存储器件写入数据并从相变存储器件读取数据。 开发者可以被配置为在存储在相变存储器件中的数据与搜索数据进行比较的搜索模式中控制从相变存储器件读取数据。

公开(公告)号：US20110096611A1

公开(公告)日：2011-04-28

申请号：US12929123

申请日：2011-01-03

Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

公开(公告)号：US07894277B2

公开(公告)日：2011-02-22

申请号：US12292890

申请日：2008-11-28

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

IPC: G11C7/00

CPC classification number: G11C13/0064 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C2013/0078 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

Abstract translation: 至少一个实施例包括非易失性存储单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器以及被配置为将数据写入到非易失性存储单元阵列中的写入单元。 写单元被配置为执行数据的写入，使得在被写入缓冲器之前，每个数据将在非易失性存储器中已经达到稳定的存储状态。

公开(公告)号：US20110026303A1

公开(公告)日：2011-02-03

申请号：US12901168

申请日：2010-10-08

Applicant: Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

Inventor： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

IPC: G11C11/00

CPC classification number: G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

Abstract translation: 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储器单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US20110024345A1

公开(公告)日：2011-02-03

申请号：US12935528

申请日：2009-03-19

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: B01D63/02 ,  B01D65/00

CPC classification number: B01D65/00 ,  B01D63/02 ,  B01D63/04 ,  B01D2313/21 ,  B01D2313/90

Abstract: A hollow fiber membrane module (200) and a puller (300) used therefore is disclosed, wherein each individual hollow fiber membrane module can be easily pulled out from a filtering apparatus provided with a plurality of hollow fiber membrane modules if it is required to be replaced or repaired. At this time, the hollow fiber membrane module (200) comprises a hollow fiber membrane (220); and at least on header (210) to which the hollow fiber membrane is potted, wherein the header (210) includes a first lateral side to which the hollow fiber membrane is potted and a second lateral side opposite to the first lateral side; and wherein an engaging plate (213) is formed at the second lateral side. Also, the puller (300) comprises a main body (310) and a hooking member (320), extending from an end of the main body, formed in a shape suitable for being caught in the engaging plate (213).

Abstract translation: 因此，公开了一种中空纤维膜组件（200）和牵引器（300），其中如果需要的话，每个单独的中空纤维膜组件可以容易地从设置有多个中空纤维膜组件的过滤装置中拔出 更换或维修。 此时，中空纤维膜组件（200）包括中空纤维膜（220）。 并且至少在封入中空纤维膜的集管（210）上，其中集管（210）包括中空纤维膜被灌封的第一侧面和与第一侧面相对的第二侧面; 并且其中在所述第二横向侧形成有接合板（213）。 此外，牵引器（300）包括从主体的端部延伸的主体（310）和钩构件（320），其形状适于卡合在接合板（213）中。

公开(公告)号：US07876609B2

公开(公告)日：2011-01-25

申请号：US12720918

申请日：2010-03-10

Applicant: Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

Inventor： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

Abstract translation: 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US07843741B2

公开(公告)日：2010-11-30

申请号：US12419934

申请日：2009-04-07

Applicant: Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

Inventor： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

IPC: G11C7/10

CPC classification number: G11C8/10 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3459 ,  G11C2013/0076

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles.

Abstract translation: 监视应用于诸如可变电阻存储器件的存储器件的选定存储器位置的多个读周期。 接收要写入所选存储单元的写入数据。 基于所监视的读取周期数，对接收的写入数据进行选择性的预写入验证和写入。 选择性地预写入验证和写入所接收的写入数据可以包括例如将接收到的写入数据写入所选择的存储器单元区域，而无需预写入验证，响应于所监视的读取周期数大于预定数量的读取周期 。

公开(公告)号：US20100103726A1

公开(公告)日：2010-04-29

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

Inventor： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。