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公开(公告)号：US20190266973A1
公开(公告)日：2019-08-29
申请号：US16408593
申请日：2019-05-10
Applicant: Microchip Technology Incorporated
Inventor： Peter K. Nagey , Mudit Gupta , Huamin Zhou
Abstract: A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.
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公开(公告)号：US10394294B2
公开(公告)日：2019-08-27
申请号：US15685719
申请日：2017-08-24
Applicant: Microchip Technology Incorporated
Inventor： Erick Pfeifer , Kyle Gaede
IPC: G06F1/20 , G06F1/32 , G06F1/3206 , G06F1/3234 , H05K7/20 , G01K7/42
Abstract: Embodiments of the present disclosure include a microcontroller configured to cool an electronic device. The microcontroller is configured to receive a power consumption value of the electronic device, determine, based on the power consumption value and a stored previous power consumption value, a change value representing an amount that power consumption of the electronic device changed from a previous power consumption of the electronic device, determine an output cooling control value based at least in part on the change value, and control an output for cooling the electronic device using the output cooling control value.
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163.发明申请公开(公告)号：US20190227976A1
公开(公告)日：2019-07-25
申请号：US16371880
申请日：2019-04-01
Applicant: Microchip Technology Incorporated
Inventor： Morten Werner Lund , Lloyd Clark , Odd Magne Reitan
IPC: G06F13/42 , G06F3/041 , G09G5/00 , G06F9/54 , G06F13/362
Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.
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164.发明申请公开(公告)号：US20190222110A1
公开(公告)日：2019-07-18
申请号：US16236507
申请日：2018-12-30
Applicant: Microchip Technology Incorporated
Inventor： Rohit Tirumala , Tommy Ho , Fu-Ho Lee , Miguel A. Salcedo
Abstract: An apparatus and method for reducing an output voltage ripple of a converter are provided. The apparatus may include a controller for controlling a converter, wherein the controller may include a clock generating circuit that generates a periodic clock signal containing periodic clock pulses, and a control circuit that causes the clock generating circuit to asynchronously initiate a clock pulse based on a difference between a feedback voltage of the converter and a reference voltage. The apparatus may also include an on-time modulation circuit which modulates the on-time based on the difference between the reference voltage and the sampled output voltage.
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165.发明授权公开(公告)号：US10347728B1
公开(公告)日：2019-07-09
申请号：US15922571
申请日：2018-03-15
Applicant: Microchip Technology Incorporated
Inventor： Mel Hymas , James Walls , Sonu Daryanani
IPC: H01L29/00 , H01L29/423 , H01L27/11521 , G11C16/08 , G11C16/04 , G11C16/14 , H01L29/78
Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.
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Patent Agency Ranking
166.发明授权公开(公告)号：US10345985B2
公开(公告)日：2019-07-09
申请号：US15613450
申请日：2017-06-05
Applicant: Microchip Technology Incorporated
Inventor： Lionel Portmann , Axel Heim , Andreas Dorfner , Claus Kaltner
Abstract: An input device has one or more electrodes configured for capacitive sensing, an electronic circuit, one or more conductive feed line(s) connecting the one or more electrode(s) with the electronic circuit, wherein the device is configured to increase or decrease a signal received from at least one of the electrodes through an associated feed line in function of at least one other signal from another electrode.
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167.发明申请公开(公告)号：US20190207034A1
公开(公告)日：2019-07-04
申请号：US15955251
申请日：2018-04-17
Applicant: Microchip Technology Incorporated
Inventor： Sonu Daryanani , James Walls , Sajid Kabeer
IPC: H01L29/788 , H01L27/11521 , H01L29/66 , H01L21/265 , H01L21/324 , H01L21/225 , H01L29/167
CPC classification number: H01L29/7884 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L27/11521 , H01L29/167 , H01L29/42328 , H01L29/66825 , H01L29/7885
Abstract: A method is provided for forming a split-gate memory cell having field enhancement regions in the substrate for improved cell performance. The method may include forming a pair of gate structures over a substrate, performing a source implant between the pair of gate structures to form a self-aligned source implant region in the substrate, performing a field enhancement implant process to form field enhancement implant regions, e.g., having an opposite dopant polarity as the source implant, at or adjacent lateral sides of the source implant region, and diffusing the source implant region and field enhancement implant regions to thereby define a source region with field enhanced regions at lateral edges of the source region. The field enhanced implant process may include at least one non-vertical angled implant.
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168.发明申请公开(公告)号：US20190199204A1
公开(公告)日：2019-06-27
申请号：US16165384
申请日：2018-10-19
Applicant: Microchip Technology Incorporated
Inventor： Santosh Manjunath Bhandarkar , Alex Dumais
CPC classification number: H02M1/4225 , G05F1/565 , H02M1/083 , H02M1/143 , H02M3/1563 , H02M3/157 , H02M7/217 , H02M2001/0019 , H02M2001/0022 , H02M2001/0032 , H02M2001/0058 , H02M2003/1566
Abstract: A circuit arrangement for switched boundary mode power conversion, a corresponding signal processor and a method of switched boundary mode power conversion are provided. The circuit arrangement comprises an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, an energy storage device, a controllable switching device, and a signal processor. The signal processor is connected to the controllable switching device and being configured for zero-current switching of the switching device. The signal processor is further configured to determine an on-time period for the switching device in one or more switching cycles based on the output voltage and the output of a crossover frequency control module to provide an improved transient response characteristic of the circuit arrangement.
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公开(公告)号：US10331604B2
公开(公告)日：2019-06-25
申请号：US15901937
申请日：2018-02-22
Applicant: Microchip Technology Incorporated
Inventor： Atish Ghosh , Rekha Edamalapati , Vinoth Sekar
Abstract: A universal serial bus (USB) hub includes an upstream port configured to be communicatively coupled to a USB host, a downstream port, and a USB hub core circuit. The circuit is configured to determine a detachment from the downstream port, determine whether a USB element has reattached to the downstream port in USB mode, and, based on a determination that the USB element has reattached to the downstream port in USB host mode, perform USB multi-host bridging for the USB host and the USB element.
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公开(公告)号：US10331513B2
公开(公告)日：2019-06-25
申请号：US15221409
申请日：2016-07-27
Applicant: Microchip Technology Incorporated
Inventor： Darren Wenn
Abstract: An integrated circuit includes comprising a cyclic redundancy check (CRC) circuit configured to read data identifying an execution path from code executed by a processor, determine a CRC check value for the data, and, based upon the CRC check value, determine whether the execution is valid.
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