公开(公告)号：US10715364B2

公开(公告)日：2020-07-14

申请号：US16353645

申请日：2019-03-14

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03 ,  H04L27/08 ,  G11C7/10 ,  H04L27/04 ,  H04B1/04 ,  H03K19/00

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10686634B2

公开(公告)日：2020-06-16

申请号：US16536179

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

IPC: H04L25/49 ,  G11C7/10

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10600745B2

公开(公告)日：2020-03-24

申请号：US16256296

申请日：2019-01-24

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H01L23/64 ,  H04L27/04 ,  H04B5/00 ,  H01L23/00 ,  H01L25/065 ,  G11C7/10 ,  G11C11/56 ,  G06F13/40 ,  G11C5/06 ,  G11C7/02 ,  G11C11/16 ,  G11C11/401 ,  G11C11/22 ,  G11C13/00

Abstract: Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

公开(公告)号：US10446198B2

公开(公告)日：2019-10-15

申请号：US15977815

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US20190295607A1

公开(公告)日：2019-09-26

申请号：US16439628

申请日：2019-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C5/14 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10

Abstract: An apparatus is disclosed. The apparatus comprises a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US20190237125A1

公开(公告)日：2019-08-01

申请号：US16375770

申请日：2019-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C11/4074 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C8/06

CPC classification number: G11C11/4074 ,  G11C5/066 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

公开(公告)号：US20190229075A1

公开(公告)日：2019-07-25

申请号：US16256296

申请日：2019-01-24

Applicant: Micron Technology, Inc

Inventor： Timothy M. Hollis

IPC: H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H04L27/04 ,  H04B5/00

Abstract: Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

公开(公告)号：US10277435B2

公开(公告)日：2019-04-30

申请号：US15870502

申请日：2018-01-12

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Feng Lin

IPC: G06F1/32 ,  H04L25/49 ,  H04L27/04 ,  G06F13/40 ,  G06F1/324 ,  G06F13/16 ,  H04L27/06

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20190102330A1

公开(公告)日：2019-04-04

申请号：US15977818

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US20190102298A1

公开(公告)日：2019-04-04

申请号：US15977808

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.