公开(公告)号：US20230066972A1

公开(公告)日：2023-03-02

申请号：US17410265

申请日：2021-08-24

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Henry Chin ,  Erika Penzo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.

公开(公告)号：US20230059837A1

公开(公告)日：2023-02-23

申请号：US17403052

申请日：2021-08-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jayavel Pachamuthu ,  Ramkumar Subramanian

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

公开(公告)号：US11587619B2

公开(公告)日：2023-02-21

申请号：US17360677

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.

公开(公告)号：US20230051815A1

公开(公告)日：2023-02-16

申请号：US17399710

申请日：2021-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Linghan Chen ,  Raghuveer S. Makala ,  Fumitaka Amano

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

公开(公告)号：US20230050955A1

公开(公告)日：2023-02-16

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

公开(公告)号：US20230042438A1

公开(公告)日：2023-02-09

申请号：US17396291

申请日：2021-08-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/32 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

公开(公告)号：US11568945B2

公开(公告)日：2023-01-31

申请号：US17343075

申请日：2021-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Anirudh Amarnath ,  Jongyeon Kim

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

公开(公告)号：US11568943B2

公开(公告)日：2023-01-31

申请号：US17102954

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/14

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

公开(公告)号：US20230023523A1

公开(公告)日：2023-01-26

申请号：US17936479

申请日：2022-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiromi MINAMITANI ,  Kei NOZAWA ,  Yusuke YOSHIDA

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524

Abstract: A three-dimensional memory device includes vertical layer stacks that are laterally spaced apart by backside trenches that laterally extend along a first horizontal direction, where each of the vertical layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stacks, memory opening fill structures located in the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and backside trench fill structures located within a respective one of the backside trenches. Each of the backside trench fill structures includes a plurality of dielectric bridge structures laterally spaced apart along the first horizontal direction and dielectric fin portions located at levels of a plurality of the electrically conductive layers. The dielectric fin portions laterally protrude outward relative to sidewalls of the insulating layers within the respective neighboring pair of alternating stacks.

公开(公告)号：US11557358B2

公开(公告)日：2023-01-17

申请号：US17231071

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.