公开(公告)号：US10276236B2

公开(公告)日：2019-04-30

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  G11C11/00 ,  H01L27/24 ,  H01L45/00

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US10269440B2

公开(公告)日：2019-04-23

申请号：US15374588

申请日：2016-12-09

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11558 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20190115088A1

公开(公告)日：2019-04-18

申请号：US16218398

申请日：2018-12-12

Applicant: Silicon STorage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/16 ,  G11C5/14 ,  G11C16/10 ,  G11C8/08

Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

公开(公告)号：US10249375B2

公开(公告)日：2019-04-02

申请号：US15987735

申请日：2018-05-23

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11558 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US10236068B2

公开(公告)日：2019-03-19

申请号：US15873872

申请日：2018-01-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28 ,  G11C16/14 ,  G11C16/24 ,  G11C7/06 ,  G11C16/04

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.

公开(公告)号：US20190080767A1

公开(公告)日：2019-03-14

申请号：US16025039

申请日：2018-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/28

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

公开(公告)号：US10199112B1

公开(公告)日：2019-02-05

申请号：US15687092

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/34

Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.

公开(公告)号：US10181354B2

公开(公告)日：2019-01-15

申请号：US15690159

申请日：2017-08-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Bin Sheng ,  Yao Zhou ,  Tao Wang ,  Xiaozhou Qian ,  Lu Guo ,  Ning Bai

IPC: G11C16/08 ,  G11C16/28 ,  G11C16/04

Abstract: The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.

公开(公告)号：US10056398B1

公开(公告)日：2018-08-21

申请号：US15945659

申请日：2018-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Nhan Do

IPC: H01L27/11521 ,  G11C16/04 ,  H01L29/423 ,  G11C16/16 ,  G11C16/10

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

公开(公告)号：US09985042B2

公开(公告)日：2018-05-29

申请号：US15489548

申请日：2017-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/306 ,  H01L21/8238 ,  H01L27/11568 ,  H01L21/3065

CPC classification number: H01L27/11568 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/823821 ,  H01L28/00

Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.