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    Photonic Wafer Level Testing Systems, Devices, and Methods of Operation
    172.
    发明申请
    Photonic Wafer Level Testing Systems, Devices, and Methods of Operation 审中-公开

    公开(公告)号：US20200033228A1

    公开(公告)日：2020-01-30

    申请号：US16048074

    申请日：2018-07-27

    Applicant: STMicroelectronics S.r.I

    Inventor： Marco Piazza ,  Antonio Canciamilla ,  Piero Orlandi ,  Luca Maggi

    IPC: G01M11/00 ,  G02B6/293 ,  G01R31/317 ,  G01R31/3185 ,  G01M11/02

    Abstract: A photonic testing device includes a substrate, an optical device under test (DUT) disposed over the substrate, and an optical input circuit disposed over the substrate. The optical input circuit includes a first plurality of inputs each configured to transmit a respective optical test signal of a plurality of optical test signals. Each of the plurality of optical test signals includes a respective dominant wavelength of a plurality of dominant wavelengths. The optical input circuit further includes an output coupled to an input waveguide of the optical DUT. The output is configured to transmit a combined optical test signal comprising the plurality of optical test signals.

    Block Made of a Building Material
    173.
    发明申请
    Block Made of a Building Material 审中-公开

    公开(公告)号：US20190271664A1

    公开(公告)日：2019-09-05

    申请号：US16415973

    申请日：2019-05-17

    Applicant: STMicroelectronics S.r.I.

    Inventor： Alberto Pagani

    IPC: G01N27/82 ,  G01N33/38 ,  G01N27/72

    Abstract: A building structure includes a block of building material and a magnetic circuit buried in the block of building material. The structure also includes a plurality of sensing devices buried in the block of building material. Each sensing device may include a contactless power supplying circuit magnetically coupled with the magnetic circuit to generate a supply voltage when the magnetic circuit is subject to a variable magnetic field.

    Row Decoding Architecture for a Phase-Change Non-Volatile Memory Device and Corresponding Row Decoding Method
    174.
    发明申请
    Row Decoding Architecture for a Phase-Change Non-Volatile Memory Device and Corresponding Row Decoding Method 审中-公开

    公开(公告)号：US20190206488A1

    公开(公告)日：2019-07-04

    申请号：US16222484

    申请日：2018-12-17

    Applicant: STMicroelectronics S.r.I.

    Inventor： Antonino Conte

    IPC: G11C13/00

    Abstract: In an embodiment, a non-volatile memory device includes a memory array divided into a plurality of tiles, and a row decoder that includes main row decoding units associated to a respective group of tiles. The row decoded further includes local row decoding units, each associated to a respective tile for carrying out selection and biasing of corresponding word lines based on decoded address signals and biasing signals. Each local row decoding unit has logic-combination modules coupled to a set of word lines and include, for each word line, a pull-down stage for selecting a word line, and a pull-up stage. The pull-up stage is dynamically biased, alternatively, in a strong-biasing condition towards a tile-supply voltage when the word line is not selected, or in a weak-biasing condition when the word line is selected.

    Pressure sensor device for measuring a differential normal pressure to the device and related methods
    177.
    发明授权
    Pressure sensor device for measuring a differential normal pressure to the device and related methods 有权

    公开(公告)号：US10041848B2

    公开(公告)日：2018-08-07

    申请号：US15644301

    申请日：2017-07-07

    Applicant: STMicroelectronics S.r.I.

    Inventor： Alessandro Motta ,  Alberto Pagani ,  Giovanni Sicurella

    IPC: G01L9/06 ,  G01L1/18 ,  G01L9/00

    Abstract: A pressure sensor device is to be positioned within a material where a mechanical parameter is measured. The pressure sensor device may include an IC having a ring oscillator with an inverter stage having first doped and second doped piezoresistor couples. Each piezoresistor couple may include two piezoresistors arranged orthogonal to one another with a same resistance value. Each piezoresistor couple may have first and second resistance values responsive to pressure. The IC may include an output interface coupled to the ring oscillator and configured to generate a pressure output signal based upon the first and second resistance values and indicative of pressure normal to the IC.

    Safe scheduler for finite state deterministic application
    180.
    发明授权
    Safe scheduler for finite state deterministic application 有权
    用于有限状态确定性应用的安全调度器

    公开(公告)号：US09558052B2

    公开(公告)日：2017-01-31

    申请号：US14218482

    申请日：2014-03-18

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.I.

    Inventor： Om Ranjan ,  Giampiero Borgonovo ,  Deepak Baranwal

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/22 ,  G06F11/30 ,  G05B19/042 ,  G05B23/02

    CPC classification number: G06F11/0736 ,  G05B19/0428 ,  G05B23/0254 ,  G05B2219/2637 ,  G06F11/2205 ,  G06F11/3013

    Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.

    Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。

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