公开(公告)号：US11742789B2

公开(公告)日：2023-08-29

申请号：US17535176

申请日：2021-11-24

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Vanni Poletto ,  Paolo Vilmercati ,  Marco Cignoli

IPC: H02P27/12 ,  H02P27/08

CPC classification number: H02P27/12 ,  H02P27/085

Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.

公开(公告)号：US11742757B2

公开(公告)日：2023-08-29

申请号：US17650463

申请日：2022-02-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

Inventor： Francois Druilhe ,  Patrik Arno ,  Alessandro Inglese ,  Michele Alessandro Carrano

IPC: H02M3/158 ,  H02M1/36 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/36 ,  H02M1/0045

Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.

公开(公告)号：US20230266381A1

公开(公告)日：2023-08-24

申请号：US17678763

申请日：2022-02-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Gaudenzia BAGNATI ,  Marzia ANNOVAZZI ,  Diego ALAGNA ,  Lucia MAGGIO

IPC: G01R31/28 ,  H03K17/687 ,  H03K21/08 ,  H03K5/24

CPC classification number: G01R31/2851 ,  H03K17/6874 ,  H03K21/08 ,  H03K5/24 ,  G01R31/52

Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.

公开(公告)号：US20230261100A1

公开(公告)日：2023-08-17

申请号：US18167623

申请日：2023-02-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando IUCOLANO ,  Andrea SEVERINO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1608 ,  H01L29/66462

Abstract: A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.

公开(公告)号：US20230259433A1

公开(公告)日：2023-08-17

申请号：US17670055

申请日：2022-02-11

Applicant: STMicroelectronics S.r.l.

Inventor： Enea Dimroci ,  Francesca Giacoma Mignemi ,  Roberta Priolo ,  Marco Leo ,  Francesco Battini

IPC: G06F11/26

CPC classification number: G06F11/26

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

公开(公告)号：US11717825B2

公开(公告)日：2023-08-08

申请号：US16231251

申请日：2018-12-21

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Davide Cucchi ,  Lorenzo Bruno ,  Francesco Ferrara

IPC: B01L3/00 ,  F16K99/00 ,  B01L7/00 ,  B01L9/00

CPC classification number: B01L3/502738 ,  B01L7/5255 ,  B01L9/527 ,  F16K99/003 ,  F16K99/0015 ,  F16K99/0046 ,  F16K99/0053 ,  B01L2200/027 ,  B01L2400/043 ,  B01L2400/0633 ,  B01L2400/0638

Abstract: The valve is formed in a valve body housing a first path portion, a second path portion, and an coupling zone between the first and second path portions. A shutter is arranged in the coupling zone and has a shutting portion of ferromagnetic material that is deformable under the action of an external magnetic field between an undeformed position, wherein the shutter closes the coupling zone, and a deformed position, wherein the shutter at least partially frees the coupling zone. The shutting portion of the shutter is formed by a rubber membrane incorporating particles, for example of ferrite particles.

公开(公告)号：US20230245699A1

公开(公告)日：2023-08-03

申请号：US18148380

申请日：2022-12-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio Enrico Carlo DISEGNI ,  Marcella CARISSIMI ,  Alessandro TOMASONI ,  Daniele LO IACONO

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.

公开(公告)号：US20230243886A1

公开(公告)日：2023-08-03

申请号：US17592171

申请日：2022-02-03

Applicant: STMicroelectronics S.r.l.

Inventor： Filippo Colombo

IPC: G01R31/316 ,  G01R31/317

CPC classification number: G01R31/316 ,  G01R31/31704

Abstract: An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

公开(公告)号：US11716061B2

公开(公告)日：2023-08-01

申请号：US17665399

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Modaffari ,  Germano Nicollini

IPC: H03F3/45 ,  H03F3/70

CPC classification number: H03F3/45273 ,  H03F3/45269 ,  H03F2203/45526

Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.

公开(公告)号：US20230234836A1

公开(公告)日：2023-07-27

申请号：US17583896

申请日：2022-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： Raffaele Enrico FURCERI ,  Luca MOLINARI

IPC: B81B7/00 ,  G02B26/08 ,  B81B3/00

CPC classification number: B81B7/008 ,  B81B3/0043 ,  G02B26/0833 ,  B81B2201/042 ,  B81B2207/03

Abstract: Techniques to be described herein are based upon the combination of a digital lock-in amplifier approach with a numerical method to yield accurate estimations of the amplitude and phase of a sense signal obtained from a movement sensor associated with a resonant MEMS device such as a MEMS mirror. The techniques described herein are efficient from a computational point of view, in a manner which is suitable for applications in which the implementing hardware is to follow size and power consumption constraints.