公开(公告)号：US20220319599A1

公开(公告)日：2022-10-06

申请号：US17223482

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Haitao Liu

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423

Abstract: Multi-gate transistors, as well as apparatus containing such multi-gate transistors and methods of forming such multi-gate transistors, might facilitate gating voltages in integrated circuit devices. Such multi-gate transistors might include an active area having a first conductivity type, a first source/drain region in the active area and having a second conductivity type different than the first conductivity type, a second source/drain region in the active area and having the second conductivity type, and a plurality of control gates adjacent the active area between the first source/drain region and the second source/drain region, wherein each control gate of the plurality of control gates comprises a respective plurality of control gate portions, and wherein, for a particular control gate of the plurality of control gates, each control gate portion of its respective plurality of control gate portions is adjacent the active area in a respective plane of a plurality of different planes.

公开(公告)号：US20220278112A1

公开(公告)日：2022-09-01

申请号：US17186962

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

IPC: H01L27/1156 ,  H01L29/24 ,  H01L29/786

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：US20220262813A1

公开(公告)日：2022-08-18

申请号：US17734410

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11417396B2

公开(公告)日：2022-08-16

申请号：US17067550

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20220238431A1

公开(公告)日：2022-07-28

申请号：US17161313

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/48

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11380699B2

公开(公告)日：2022-07-05

申请号：US16288982

申请日：2019-02-28

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H01L27/11556 ,  H01L27/1157 ,  G11C5/06 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11582

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US11348932B2

公开(公告)日：2022-05-31

申请号：US16810009

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11335404B2

公开(公告)日：2022-05-17

申请号：US17080553

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20220122998A1

公开(公告)日：2022-04-21

申请号：US17561579

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  H01G4/33 ,  H01G4/40 ,  H01G4/008 ,  H01G4/08 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US20220069124A1

公开(公告)日：2022-03-03

申请号：US17524653

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L27/108 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.