公开(公告)号：US20190108108A1

公开(公告)日：2019-04-11

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20190035461A1

公开(公告)日：2019-01-31

申请号：US16124222

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US20190018618A1

公开(公告)日：2019-01-17

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US20180129575A1

公开(公告)日：2018-05-10

申请号：US15345862

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/2094 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20170315734A1

公开(公告)日：2017-11-02

申请号：US15144141

申请日：2016-05-02

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F9/4411 ,  G06F13/10 ,  G06F13/1668

Abstract: A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to detect a known state to enter based, at least in part, on communication with a host device, and reconfigure the memory device to prepare for the known state. A host controller is configured to communicate with the memory device to support a feature and protocol for detecting the known state for operation of the memory device. Related methods and systems are also disclosed.

公开(公告)号：US20160364179A1

公开(公告)日：2016-12-15

申请号：US15246735

申请日：2016-08-25

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0679 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US20160231932A1

公开(公告)日：2016-08-11

申请号：US15131447

申请日：2016-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。

公开(公告)号：US20150212738A1

公开(公告)日：2015-07-30

申请号：US14605593

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： GIUSEPPE D'ELISEO ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

Abstract translation: 公开了用于在存储器中执行多个排队任务的方法和装置。 一个示例性设备包括被配置为耦合到主机的存储器。 存储器还被配置为从主机接收多个存储器访问请求，状态请求和执行命令，并且响应于来自主机的执行命令来执行多个存储器访问请求中的一个或多个。 执行命令包括与多个存储器访问请求的每个相应存储器访问请求对应的多个相应指示，并且指示主机是否请求存储器执行每个相应的存储器访问请求。

公开(公告)号：US20140201473A1

公开(公告)日：2014-07-17

申请号：US13739453

申请日：2013-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。