公开(公告)号：US10460810B2

公开(公告)日：2019-10-29

申请号：US15687191

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

公开(公告)号：US20190272876A1

公开(公告)日：2019-09-05

申请号：US16417518

申请日：2019-05-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/32 ,  G11C16/28 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.

公开(公告)号：US20190237142A1

公开(公告)日：2019-08-01

申请号：US16382034

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  H01L27/11517 ,  G06N3/04

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

公开(公告)号：US10312248B2

公开(公告)日：2019-06-04

申请号：US14935201

申请日：2015-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  G11C16/14 ,  G11C16/26 ,  H01L29/423 ,  H01L29/788

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

公开(公告)号：US20190164617A1

公开(公告)日：2019-05-30

申请号：US15826345

申请日：2017-11-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Steven Lemke ,  Santosh Hariharan ,  Stanley Hong

IPC: G11C16/34 ,  G11C16/10

Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

公开(公告)号：US10249631B2

公开(公告)日：2019-04-02

申请号：US15945161

申请日：2018-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

公开(公告)号：US20190080753A1

公开(公告)日：2019-03-14

申请号：US15701071

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.

公开(公告)号：US10141062B2

公开(公告)日：2018-11-27

申请号：US15135445

申请日：2016-04-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Viet Tan Nguyen

IPC: G11C11/34 ,  G11C7/02 ,  G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C8/10 ,  G11C5/14 ,  G11C16/32 ,  G11C29/14

Abstract: A circuit and method are disclosed for operating a non-volatile memory device, comprising time sampling a reference current or voltage in a floating holding node to obtain a hold voltage and applying the hold voltage in sensing circuitry.

公开(公告)号：US10134475B2

公开(公告)日：2018-11-20

申请号：US15048707

申请日：2016-02-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/24 ,  G11C16/14 ,  G11C16/12 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/16

Abstract: Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.

公开(公告)号：US20180204627A1

公开(公告)日：2018-07-19

申请号：US15924100

申请日：2018-03-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.