公开(公告)号：US20200065252A1

公开(公告)日：2020-02-27

申请号：US16666740

申请日：2019-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0875 ,  G06F9/38 ,  G06F9/345 ,  G06F9/32 ,  G06F9/30 ,  G06F12/0897

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

公开(公告)号：US10387354B2

公开(公告)日：2019-08-20

申请号：US16155047

申请日：2018-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Sureshkumar Govindaraj

IPC: G06F13/42 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F15/78 ,  G06F15/76 ,  H04N19/423

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

公开(公告)号：US20190073222A1

公开(公告)日：2019-03-07

申请号：US16126680

申请日：2018-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/0811 ,  G06F11/00 ,  G06F9/345 ,  G06F9/32 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

公开(公告)号：US10203958B2

公开(公告)日：2019-02-12

申请号：US15635409

申请日：2017-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/312 ,  G06F9/34 ,  G06F12/12 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

公开(公告)号：US20190042517A1

公开(公告)日：2019-02-07

申请号：US16155047

申请日：2018-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Sureshkumar Govindaraj

IPC: G06F13/42 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F15/78

CPC classification number: G06F13/42 ,  G06F9/30145 ,  G06F9/3802 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/7807 ,  G06F2212/452 ,  H04N19/423

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

公开(公告)号：US20190026111A1

公开(公告)日：2019-01-24

申请号：US16139858

申请日：2018-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F12/0897 ,  G06F9/30 ,  G06F13/40 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/345

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20190004853A1

公开(公告)日：2019-01-03

申请号：US15636686

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Joseph Zbiciak

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

公开(公告)号：US20190004797A1

公开(公告)日：2019-01-03

申请号：US15635449

申请日：2017-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

公开(公告)号：US20180300133A1

公开(公告)日：2018-10-18

申请号：US16018234

申请日：2018-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

公开(公告)号：US10083035B2

公开(公告)日：2018-09-25

申请号：US15384580

申请日：2016-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/34 ,  G06F12/00 ,  G06F13/36 ,  G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0815 ,  G06F9/345

CPC classification number: G06F9/321 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0207 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/1605 ,  G06F13/4068 ,  G06F2212/452 ,  G06F2212/60

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.