公开(公告)号：US11004846B2

公开(公告)日：2021-05-11

申请号：US16891992

申请日：2020-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

公开(公告)号：US10998226B2

公开(公告)日：2021-05-04

申请号：US16206768

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/485

Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.

公开(公告)号：US10777419B2

公开(公告)日：2020-09-15

申请号：US16243242

申请日：2019-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31

Abstract: A fin strip is formed over a substrate using a hardmask. The fin strip includes a first portion and a second portion laterally adjoining the first portion. A BARC layer is formed to cover the fin strip over the substrate. A first etching operation is performed to remove a first portion of the BARC layer, so as to expose a portion of the hardmask where the first portion of the fin strip underlies. A coating layer is deposited over the portion of the hardmask and the BARC layer. A second etching operation is performed to remove a portion of the coating layer, the portion of the hardmask and a second portion of the BARC layer. A third etching operation is performed to remove the first portion of the fin strip and a remaining BARC layer, such that the second portion of the fin strip forms a plurality of semiconductor fins.

公开(公告)号：US10700180B2

公开(公告)日：2020-06-30

申请号：US16047038

申请日：2018-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/027 ,  H01L21/321

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap.

公开(公告)号：US10535603B2

公开(公告)日：2020-01-14

申请号：US15895895

申请日：2018-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

Abstract: A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.

公开(公告)号：US20190386003A1

公开(公告)日：2019-12-19

申请号：US16524142

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

公开(公告)号：US10510866B1

公开(公告)日：2019-12-17

申请号：US16007885

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/08 ,  H01L21/02 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.

公开(公告)号：US10431687B2

公开(公告)日：2019-10-01

申请号：US15687723

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

公开(公告)号：US10396184B2

公开(公告)日：2019-08-27

申请号：US15885036

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Chiang Hung ,  Wei-Hao Huang

IPC: H01L31/072 ,  H01L31/0328 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

公开(公告)号：US10366990B2

公开(公告)日：2019-07-30

申请号：US15627329

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.