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公开(公告)号：US20190067293A1
公开(公告)日：2019-02-28
申请号：US15712133
申请日：2017-09-21
Inventor： Ger-Pin Lin , Kuan-Chun Lin , Chi-Mao Hsu , Shu-Yen Chan , Shih-Fang Tzou , Tsuo-Wen Lu , Tien-Chen Chan , Feng-Yi Chang , Shih-Kuei Yen , Fu-Che Lee
IPC: H01L27/108 , H01L21/28
Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
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公开(公告)号：US20190057967A1
公开(公告)日：2019-02-21
申请号：US16027267
申请日：2018-07-04
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , G11C11/404 , G11C11/4074 , G11C7/02 , H01L49/02
CPC classification number: H01L27/10814 , G11C7/02 , G11C11/404 , G11C11/4074 , H01L27/10823 , H01L27/10852 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/90
Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
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公开(公告)号：US10192777B2
公开(公告)日：2019-01-29
申请号：US15854765
申请日：2017-12-27
Inventor： Hsien-Shih Chu , Ming-Feng Kuo , Yi-Wang Zhan , Li-Chiang Chen , Fu-Che Lee , Feng-Yi Chang
IPC: H01L21/762 , H01L29/06 , H01L21/308 , H01L21/3065 , H01L21/02
Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.
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公开(公告)号：US20180374702A1
公开(公告)日：2018-12-27
申请号：US15660967
申请日：2017-07-27
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L21/033 , H01L21/3213
CPC classification number: H01L21/0337 , H01L21/0332 , H01L21/32139 , H01L27/10894
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
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公开(公告)号：US10147726B1
公开(公告)日：2018-12-04
申请号：US15629768
申请日：2017-06-22
Inventor： Feng-Yi Chang , Fu-Che Lee
IPC: H01L27/108 , H01L23/535
Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
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Patent Agency Ranking
公开(公告)号：US10141223B2
公开(公告)日：2018-11-27
申请号：US15869107
申请日：2018-01-12
Inventor： Li-Chiang Chen , Fu-Che Lee , Ming-Feng Kuo
IPC: H01L21/768 , H01L21/321 , H01L21/3213 , H01L27/108 , H01L21/285 , H01L21/3105
Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.
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公开(公告)号：US20180294188A1
公开(公告)日：2018-10-11
申请号：US15869107
申请日：2018-01-12
Inventor： Li-Chiang Chen , Fu-Che Lee , Ming-Feng Kuo
IPC: H01L21/768 , H01L21/321 , H01L21/3213 , H01L21/3105 , H01L27/108 , H01L21/285
CPC classification number: H01L21/76877 , H01L21/28568 , H01L21/31058 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L27/10891
Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.
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178.发明申请公开(公告)号：US20180240705A1
公开(公告)日：2018-08-23
申请号：US15472295
申请日：2017-03-29
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Fu-Che Lee , Ming-Feng Kuo
IPC: H01L21/768 , H01L21/762 , H01L21/311 , H01L21/02 , H01L23/535 , H01L29/06
CPC classification number: H01L21/76895 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76224 , H01L21/76805 , H01L21/76814 , H01L21/76849 , H01L23/528 , H01L23/535 , H01L27/10888 , H01L29/0649
Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
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公开(公告)号：US20180233451A1
公开(公告)日：2018-08-16
申请号：US15466881
申请日：2017-03-23
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L23/535 , H01L21/768 , H01L21/3213
CPC classification number: H01L27/10894 , H01L21/76885 , H01L21/76895 , H01L27/10814 , H01L27/10855
Abstract: A method for fabricating a pad structure includes the steps of: providing a material layer; forming an opening in the material layer; forming a conductive layer on the material layer and into the opening; forming a patterned mask on the conductive layer; performing a first etching process to remove part of the conductive layer for forming a conductive plug; and performing a shaping process to alter the shape of a top surface of the conductive plug.
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公开(公告)号：US10032631B1
公开(公告)日：2018-07-24
申请号：US15591132
申请日：2017-05-10
Inventor： Li-Chiang Chen , Fu-Che Lee , Ming-Feng Kuo , Hsien-Shih Chu , Cheng-Yu Wang , Yu-Chen Chuang
Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.
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