公开(公告)号：US06995060B2

公开(公告)日：2006-02-07

申请号：US10393202

申请日：2003-03-19

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S438/975

Abstract: A structure is obtained having a semiconductor substrate, the structure having an upward protruding feature (140). A first layer (160) is formed on the structure. The first layer (160) has a first portion (170.1) protruding upward over the protruding feature (140). Then a second layer (1710) is formed over the first layer (160) such that the first portion (170.1) is exposed and not completely covered by the second layer (1710). The first layer (160) is partially removed selectively to the second layer to form a cavity (1810) at the location of the first feature (140). A third layer (1910) is formed in the cavity. Then at least parts of the second layer (1710) and the first layer (160) are removed selectively to the third layer (1910). In some embodiments, self-aligned features are formed from the first layer (160) over the sidewalls of the first features (140) as a result.

Abstract translation: 获得具有半导体衬底的结构，该结构具有向上突出的特征（140）。 在该结构上形成第一层（160）。 第一层160具有在突出特征140上向上突出的第一部分170.1）。 然后在第一层（160）上形成第二层（1710），使得第一部分（170.1）暴露并不完全被第二层（1710）覆盖。 选择性地将第一层（160）部分地移除到第二层以在第一特征（140）的位置处形成空腔（1810）。 在空腔中形成第三层（1910）。 然后，选择性地将第二层（1710）和第一层（160）的至少一部分去除到第三层（1910）。 在一些实施例中，结果是在第一特征（140）的侧壁上从第一层（160）形成自对准特征。

公开(公告)号：US06975916B2

公开(公告)日：2005-12-13

申请号：US09900165

申请日：2001-07-09

Applicant: Neal Kuo

Inventor： Neal Kuo

IPC: G06Q10/00 ,  G06F19/00

CPC classification number: G06Q10/04

Abstract: A computer-implemented method for identifying the best process path in a semiconductor manufacturing process for processing a plurality of wafer lots that includes providing a plurality of operations in the semiconductor manufacturing process, providing a plurality of tools in at least one of the plurality of operations, providing a plurality of yields for each of the plurality of operations, providing a plurality of process paths, calculating an average yield for the plurality of yields, setting the average yield as a response, setting the plurality of operations as control factors, setting the plurality of tools as factor levels in response to at least one of the plurality of operations, determining at least one of the plurality of operations as having the most contribution using an analysis of variance method, wherein the at least one of the plurality of operations causes the responses to change greater than a predetermined level when the plurality of tools are changed, and outputting the at least one of the plurality of operations as the most influential operation.

Abstract translation: 一种用于识别用于处理多个晶片批次的半导体制造工艺中的最佳工艺路径的计算机实现的方法，其包括在所述半导体制造工艺中提供多个操作，在所述多个操作中的至少一个中提供多个工具 为多个操作中的每个操作提供多个产量，提供多个处理路径，计算多个产量的平均收益率，将平均收益率设置为响应，将多个操作设置为控制因素，将 多个工具作为响应于所述多个操作中的至少一个操作的因子级别，使用方差分析方法将所述多个操作中的至少一个确定为具有最多贡献，其中所述多个操作中的至少一个导致 当多个工具改变时响应变化大于预定水平，并且输出 将所述多个操作中的至少一个作为最有影响力的操作。

公开(公告)号：US20050212025A1

公开(公告)日：2005-09-29

申请号：US10962612

申请日：2004-10-13

Applicant: Yung-Nien Teng

Inventor： Yung-Nien Teng

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10873

Abstract: A memory device with an array of memory cells is described. Each memory cell comprises a deep trench capacitor and an active area. The deep trench capacitor is formed in a semiconductor substrate, and includes a node electrode and a buried electrode. The active area is formed on the semiconductor substrate, electrically connecting the node electrode and a bit line. The active area substantially has an average tunnel width along a current direction of the device. The deep trench capacitor overlaps the active area, at which the active area has an intersection width larger than the average tunnel width at the boundary.

Abstract translation: 描述了具有存储器单元阵列的存储器件。 每个存储单元包括深沟槽电容器和有源区。 深沟槽电容器形成在半导体衬底中，并且包括节点电极和埋入电极。 有源区形成在半导体衬底上，电连接节点电极和位线。 有源区域基本上具有沿器件的当前方向的平均隧道宽度。 有效区域的深沟槽电容器与有效区域重叠，在该区域的交点宽度大于边界处的平均隧道宽度。

公开(公告)号：US20050151178A1

公开(公告)日：2005-07-14

申请号：US10749771

申请日：2003-12-30

Applicant: James Shyu ,  Hsi-Chieh Chen ,  Chuan-Chi Chen

Inventor： James Shyu ,  Hsi-Chieh Chen ,  Chuan-Chi Chen

IPC: H01L21/314 ,  H01L21/318 ,  H01L21/32 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10829 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/32 ,  H01L27/10867 ,  H01L29/945

Abstract: A method for manufacturing a trench capacitor that comprises defining a semiconductor substrate, forming a trench with a lower region and an upper region in the semiconductor substrate, forming a buried conductive region around the lower region, forming a first insulating layer along sidewalls of the trench up to a level between the lower region and the upper region, forming a second insulating layer along the sidewalls of the trench at the upper region, the second insulating layer being separated from the first insulating layer by an intermediate region, and forming an oxide on the sidewalls of the trench at the intermediate region.

Abstract translation: 一种制造沟槽电容器的方法，包括限定半导体衬底，在半导体衬底中形成具有下部区域和上部区域的沟槽，在下部区域周围形成掩埋导电区域，沿着沟槽的侧壁形成第一绝缘层 直到下部区域和上部区域之间的水平面，在上部区域沿着沟槽的侧壁形成第二绝缘层，第二绝缘层通过中间区域与第一绝缘层分离，并且形成氧化物 在中间区域的沟槽的侧壁。

公开(公告)号：US06902982B2

公开(公告)日：2005-06-07

申请号：US10681125

申请日：2003-10-09

Applicant: Shih-Fang Chen

Inventor： Shih-Fang Chen

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.

Abstract translation: 用于防止寄生泄漏的沟槽电容器工艺。 该过程能够阻挡来自与沟槽相邻的寄生晶体管的漏电流，并且包括以下步骤：形成掺杂层和覆盖沟槽的侧壁部分的覆盖层，并对掺杂层执行退火处理以形成 掺杂剂区域，并且阻挡来自与沟槽相邻的寄生晶体管的泄漏电流。

公开(公告)号：US06872664B2

公开(公告)日：2005-03-29

申请号：US10600699

申请日：2003-06-23

Applicant: Yung Hsien Wu

Inventor： Yung Hsien Wu

IPC: H01L21/28 ,  H01L21/318 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/302

CPC classification number: H01L21/823462 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/3185 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device includes providing a wafer substrate having a surface, forming a first nitride layer over the wafer substrate, providing a layer of photoresist over the first nitride layer, patterning and defining the photoresist layer, etching the first nitride layer unmasked by the photoresist to remove at least a portion of the first nitride layer to expose at least a portion of the substrate surface, removing the photoresist layer, and depositing a second nitride layer over the first nitride layer and the exposed substrate surface to form a nitride structure having a first thickness and a second thickness, wherein the first thickness includes a thickness of the first nitride layer.

Abstract translation: 制造半导体器件的方法包括提供具有表面的晶片衬底，在晶片衬底上形成第一氮化物层，在第一氮化物层上提供一层光致抗蚀剂，图案化和限定光致抗蚀剂层，蚀刻第一氮化物层未屏蔽 通过所述光致抗蚀剂去除所述第一氮化物层的至少一部分以暴露所述衬底表面的至少一部分，去除所述光致抗蚀剂层，以及在所述第一氮化物层和所述暴露的衬底表面上沉积第二氮化物层以形成氮化物 结构具有第一厚度和第二厚度，其中第一厚度包括第一氮化物层的厚度。

公开(公告)号：US20040067654A1

公开(公告)日：2004-04-08

申请号：US10265826

申请日：2002-10-07

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： Chun-Wei Chen ,  Hong-Long Chang ,  Nien-Yu Tsai

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/3065

Abstract: The present invention relates to a method of reducing needle-like defects generated on a wafer rim in an etching process, wherein the etching process using both a photoresist material and hardmask material as a mask. After removing the photoresist material and the hardmask material, said method comprising the steps of: (i) depositing the photoresist material on the wafer again; (ii) performing wafer edge exposure (WEE) to form a ring of the wafer edge; and (iii) performing dry etching to the exposed ring of wafer edge to remove the needle-like defects generated on the wafer edge.

Abstract translation: 本发明涉及一种在蚀刻工艺中减少在晶片边缘上产生的针状缺陷的方法，其中使用光致抗蚀剂材料和硬掩模材料两者的蚀刻工艺作为掩模。 在去除光致抗蚀剂材料和硬掩模材料之后，所述方法包括以下步骤：（i）再次将光致抗蚀剂材料沉积在晶片上; （ii）进行晶片边缘曝光（WEE）以形成晶片边缘的环; 和（iii）对暴露的晶片边缘的环进行干蚀刻以去除在晶片边缘上产生的针状缺陷。

公开(公告)号：US20030087517A1

公开(公告)日：2003-05-08

申请号：US09993749

申请日：2001-11-06

Applicant: ProMOS Technologies, Inc.

Inventor： Brian Lee

IPC: H01L021/4763

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10888

Abstract: A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer. The bit line contact openings, substrate contact openings, and gate contact openings are filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.

Abstract translation: 描述了在DRAM集成电路器件的制造中的固结结接点蚀刻。 半导体器件结构设置在衬底中和衬底上，其中衬底被分为有源区域和外围区域。 半导体器件结构被蚀刻停止层覆盖。 介电层沉积在蚀刻停止层上。 介电层同时蚀刻穿过有源区域，以形成位线接触开口，在周边区域形成衬底接触开口，并形成栅极接触开口，其中蚀刻在蚀刻停止层处停止。 蚀刻停止层通过基板接触开口和位线接触开口被蚀刻到较小程度，而不是通过栅极接触开口。 然后，通过使用对蚀刻停止层选择性的定向蚀刻蚀刻蚀刻停止层。 位线接触开口，基板接触开口和栅极接触开口填充有导电层，以在DRAM集成电路器件的制造中完成触点的形成。

公开(公告)号：US20030064598A1

公开(公告)日：2003-04-03

申请号：US10195355

申请日：2002-07-15

Applicant: ProMOS Technologies, Inc.

Inventor： Jesse Chung ,  Hsiao-Lei Wang ,  Hung-Kwei Liao

IPC: H01L021/311

CPC classification number: H01L27/10867 ,  H01L21/743

Abstract: A method of forming a buried strap comprising the following sequential steps. A substrate having a pad oxide layer formed thereover is provided. A masking layer is formed over the pad oxide layer. The masking layer, pad oxide layer and substrate are etched to form a trench within the substrate. The trench having an outer sidewall and an upper portion. The upper portion of the trench is lined with a collar. A poly plate is formed within the trench. The poly plate and collar are etched below the substrate to form a recessed poly plate and a recessed collar and exposing a portion of outer sidewall of trench. Ions are implanted into the substrate through exposed outer sidewall of trench by gas phase doping. A SiN sidewall layer is formed over the exposed outer sidewall of trench at a temperature sufficient to diffuse the implanted ions further into the substrate to form the buried strap.

Abstract translation: 一种形成掩埋带的方法，包括以下顺序步骤。 提供了具有形成在其上的衬垫氧化物层的衬底。 在衬垫氧化物层上形成掩模层。 蚀刻掩模层，衬垫氧化物层和衬底以在衬底内形成沟槽。 沟槽具有外侧壁和上部。 沟槽的上部衬有一个领。 在沟槽内形成多晶硅板。 多晶板和套环被蚀刻在基底下方以形成凹入的多晶硅板和凹入的套环，并暴露沟槽外侧壁的一部分。 通过气相掺杂，通过暴露的沟槽的外侧壁将离子注入到衬底中。 在足以将注入的离子进一步扩散到衬底中以形成掩埋带的温度下，在沟槽的暴露的外侧壁上形成SiN侧壁层。

公开(公告)号：US20020176972A1

公开(公告)日：2002-11-28

申请号：US10145718

申请日：2002-05-16

Applicant: ProMOS Technologies, Inc.

Inventor： Tsung-Liang Tsai

IPC: B32B003/00

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L2924/3011 ,  Y10T428/24843

Abstract: The present invention provides a structure of a contact chain comprising a substrate of a first conductive type, a dielectric layer on the substrate, a plurality of contact structures and two probe pads. The contact structures are connected in series and have two ends. Each contact structure comprises a contact hole in the dielectric layer and conductive material in the contact hole, for electrically contacting with a first doped layer of a second conductive type. The first doped region is formed on the substrate. Two probe pads are coupled to the two ends, respectively. The contact chain further comprises a means for selectively coupling the first doped layer to the substrate. When the first doped layer is not coupled to the substrate, the total resistance of the contact chain can be measured through the two probe pads. During FIB failure analysis, the first doped layer can be forced to couple to the substrate, such that the PN junction between the first doped layer and the substrate will not interfere with the analytic process.