公开(公告)号：US20080048735A1

公开(公告)日：2008-02-28

申请号：US11766275

申请日：2007-06-21

Applicant: Saurabh SAXENA

Inventor： Saurabh SAXENA

IPC: H02J4/00

CPC classification number: H03K19/0005 ,  H03K17/145

Abstract: A CMOS Output Buffer providing controlled output impedance includes three internal sections each of which provides a impedance control for a corresponding region of the output V-I characteristics of deep linear, deep saturation and transition regions. Each internal section includes controlled current sinks/current sources enabled to provide a precise control over the DC impedance of the driver across the PAD voltage range.

Abstract translation: 提供受控输出阻抗的CMOS输出缓冲器包括三个内部部分，每个内部部分为深线性，深度饱和和过渡区域的输出V-I特性的对应区域提供阻抗控制。 每个内部部分包括受控的电流吸收/电流源，可以在PAD电压范围内精确控制驱动器的直流阻抗。

公开(公告)号：US07333536B2

公开(公告)日：2008-02-19

申请号：US10683887

申请日：2003-10-09

Applicant: Sangeeta Sinha ,  Praveen Kumar

Inventor： Sangeeta Sinha ,  Praveen Kumar

IPC: H04B17/00

CPC classification number: H04L25/0262

Abstract: A microcontroller with embedded software for automatically detecting a baud rate of an asynchronous serial bit stream during an initial set up phase of a microcontroller. The microcontroller is configured to receive a data set from a transmitter and includes a transition detector for identifying bit transitions in the data set. The microcontroller includes a timer triggered by the transition detector that is measures the time interval between two predefined bit transitions, a storage element for registering the measured time interval, and a look up table that provides defines baud rates relative to various time intervals that can be accessed to determine a nearest baud rate value corresponding to the registered time interval.

Abstract translation: 具有嵌入式软件的微控制器，用于在微控制器的初始设置阶段期间自动检测异步串行位流的波特率。 微控制器被配置为从发射机接收数据组，并且包括用于识别数据组中的位转换的转换检测器。 微控制器包括由转换检测器触发的定时器，该定时器测量两个预定义位转换之间的时间间隔，用于记录所测量的时间间隔的存储元件，以及提供相对于各种时间间隔定义波特率的查找表 被访问以确定对应于注册的时间间隔的最近的波特率值。

公开(公告)号：US07332978B2

公开(公告)日：2008-02-19

申请号：US11303344

申请日：2005-12-16

Applicant: Naveen Tiwari ,  Balwant Singh

Inventor： Naveen Tiwari ,  Balwant Singh

IPC: H03B27/00

CPC classification number: G06F1/04 ,  H03K3/0315 ,  H03K3/70

Abstract: A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

Abstract translation: 无毛刺控制环形振荡器可以包括连接到门控和反相器级或装置的可编程延迟链。 可以在延迟链和门控和反相器级之间提供锁存或锁存装置，或者用于在禁止振荡器并将振荡器的输出设置为注册时钟状态时注册时钟状态的装置。

公开(公告)号：US20080040713A1

公开(公告)日：2008-02-14

申请号：US11606644

申请日：2006-11-29

Applicant: Sriharsha Subbakrishna ,  Naresh Gupta ,  Mohan Kashivasi

Inventor： Sriharsha Subbakrishna ,  Naresh Gupta ,  Mohan Kashivasi

IPC: G06F9/44

CPC classification number: G06F8/65

Abstract: An embodiment of the present invention provides a system and method for remotely upgrading the firmware of a target device using wireless technology from the Bluetooth-enabled PC or Laptop to another Bluetooth device e.g., mouse, Keyboard, headset, mobile phone etc. Existing solutions either may not have upgrade capabilities, or may require the use of proprietary cables. An embodiment of the solution proposed here extends the “Connecting without cables” concept of Bluetooth to firmware upgrades. The system comprises a host device for sending the firmware required for upgradation; and a target device containing a first code and a second code wherein said first code identifies details of the firmware; and said second code identifies the completion of the download operation when the firmware is successfully downloaded.

Abstract translation: 本发明的一个实施例提供一种用于使用无线技术将蓝牙功能的PC或笔记本电脑远程升级到另一蓝牙设备（例如鼠标，键盘，耳机，移动电话等）的目标设备的固件的系统和方法。现有的解决方案 可能没有升级功能，或可能需要使用专有电缆。 这里提出的解决方案的一个实施例将蓝牙的“无电缆连接”概念扩展到固件升级。 该系统包括用于发送升级所需的固件的主机设备; 以及包含第一代码和第二代码的目标设备，其中所述第一代码识别固件的细节; 并且所述第二代码在固件被成功下载时识别下载操作的完成。

公开(公告)号：US07327300B1

公开(公告)日：2008-02-05

申请号：US11510259

申请日：2006-08-25

Applicant: Nitin Agarwal

Inventor： Nitin Agarwal

IPC: H03M1/82

CPC classification number: H03K7/08 ,  H03M1/661 ,  H03M1/822

Abstract: A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.

Abstract translation: 系统和方法产生具有可变占空比分辨率的脉宽调制信号。 硬件使用最小的硬件来将PWM占空比分辨率提高到0，从而可以获得最高可能的波形分辨率，包括正弦波。 本发明的实施例使用微控制器，W计数器除法，延迟电路，触发器和逻辑门。

公开(公告)号：US07321520B2

公开(公告)日：2008-01-22

申请号：US11394874

申请日：2006-03-31

Applicant: Swapnil Bahl ,  Balwant Singh

Inventor： Swapnil Bahl ,  Balwant Singh

IPC: G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/063

Abstract: A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for counting the locations for reading the stored data. The read address counter includes a comparator for generating a synchronous reset for itself. A selector is connected to the comparator for selecting a user defined FIFO length, or a pre-programmed write address counter length.

Abstract translation: 可配置长度先进先出（FIFO）存储器包括用于存储数据的存储器核心，连接到存储器核心的写地址计数器，用于计数用于写入要存储的数据的位置，以及连接到存储器的读地址计数器 用于计数读取存储数据的位置的核心。 读地址计数器包括用于自身产生同步复位的比较器。 选择器连接到比较器，用于选择用户定义的FIFO长度，或预编程的写入地址计数器长度。

公开(公告)号：US07282971B2

公开(公告)日：2007-10-16

申请号：US11319756

申请日：2005-12-27

Applicant: Ashish Panpalia ,  Puneet Sareen

Inventor： Ashish Panpalia ,  Puneet Sareen

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/095

Abstract: A digital delay locked loop architecture is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit which monitors the frequency of the input clock and then sets a division factor for a reference clock used to control delay tap selection. In this way, the architecture can support a fast locking time, coarse tuning and fine-tuning.

Abstract translation: 数字延迟锁定环架构独立于反馈延迟（时钟树延迟）。 该架构使用频率检测器电路，其监视输入时钟的频率，然后设置用于控制延迟分接选择的参考时钟的分频因子。 以这种方式，架构可以支持快速锁定时间，粗调和微调。

公开(公告)号：US07266005B2

公开(公告)日：2007-09-04

申请号：US11321794

申请日：2005-12-29

Applicant: Danish Hasan Syed ,  Rajiv Kumar Yadav ,  Anoop Khurana

Inventor： Danish Hasan Syed ,  Rajiv Kumar Yadav ,  Anoop Khurana

IPC: G11C27/00

CPC classification number: G11C15/00 ,  H04L45/00 ,  H04L45/54 ,  H04L45/7453 ,  H04L45/7457

Abstract: An efficient Content Addressable Memory array for Classless Inter-Domain Routing with each CAM cell including an additional storage unit for storing the prefix length associated with the contents of the cell. An enabling logic connects the prefix length value to a wired OR plane common to all CAM cells, and a sequential bit wise comparison unit has its inputs connected to the wired OR plane and the additional storage unit with its output controlling the enabling logic.

Abstract translation: 用于无类别域间路由的高效内容可寻址存储器阵列，每个CAM单元包括用于存储与该单元的内容相关联的前缀长度的附加存储单元。 启用逻辑将前缀长度值连接到所有CAM单元共有的有线OR平面，并且顺序比特单元的输入连接到有线OR平面，附加存储单元的输出控制使能逻辑。

公开(公告)号：US20070201287A1

公开(公告)日：2007-08-30

申请号：US11617286

申请日：2006-12-28

Applicant: Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

IPC: G11C7/00

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized. the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract translation: 公开了一种用于引入自定时存储器中的延迟的新方法。 在所提出的方法中，通过在要延迟的信号的路径上引入电容来引入延迟。 电容通过在电路中使用空闲的躺着金属层来实现。 要延迟的信号通过可编程开关连接到这些空闲的电平。 引入的延迟量取决于信号路径中引入的电容，又依赖于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于在所提出的方法中，利用空闲的金属电容。 该电路可以使用最小量的附加硬件来实现。 由所提出的电路提供的延迟也是存储器单元香料特性和核心寄生电容的函数。

公开(公告)号：US20070200617A1

公开(公告)日：2007-08-30

申请号：US11618116

申请日：2006-12-29

Applicant: Ashish Kumar

Inventor： Ashish Kumar

IPC: G05F1/10

CPC classification number: H03K19/0016

Abstract: An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to the value of a standby signal and an input signal. The standby signal is high in the standby mode and low in the active mode.

Abstract translation: 使用门控电源减少半导体器件的漏电元件的架构是基于电源分为两部分。 另一个逆变器连接到由同一单个电源轨道导出的不同电源轨。 根据待机信号和输入信号的值，启用和禁用电源轨。 待机信号在待机模式为高电平，低电平有效。