公开(公告)号：US20080094120A1

公开(公告)日：2008-04-24

申请号：US11906368

申请日：2007-10-01

Applicant: Rosario Scollo ,  Massimo Nania

Inventor： Rosario Scollo ,  Massimo Nania

IPC: H03K17/04

CPC classification number: H03K17/567 ,  H03K17/0412

Abstract: An embodiment of the invention relates to a driving circuit for an emitter-switching configuration of transistors having at least one first and one second control terminal connected to the driving circuit to form a controlled emitter-switching device having in turn respective collector, source and gate terminals. Advantageously the driving circuit comprises at least one IGBT device inserted between the collector terminal and a first end of a capacitor, whose second end is connected to the first control terminal, the IGBT device having in turn a third control terminal connected, through a first resistive element, to the gate terminal, as well as a second resistive element inserted between the gate terminal and the second control terminal. Advantageously, the driving circuit further comprises an additional supply inserted between the first and second ends of the capacitor to ensure its correct biasing.

Abstract translation: 本发明的一个实施例涉及一种用于晶体管的发射极 - 开关配置的驱动电路，其具有连接到驱动电路的至少一个第一和第二控制端，以形成受控的发射极开关器件，其具有依次分别的集电极，源极和栅极 终端。 有利地，驱动电路包括插入在集电极端子和电容器的第一端之间的至少一个IGBT器件，其第二端连接到第一控制端子，所述IGBT器件依次通过第一电阻器连接第三控制端子 元件，到栅极端子，以及插入在栅极端子和第二控制端子之间的第二电阻元件。 有利地，驱动电路还包括插入在电容器的第一和第二端之间的附加电源，以确保其正确的偏置。

公开(公告)号：US20080018383A1

公开(公告)日：2008-01-24

申请号：US11780206

申请日：2007-07-19

Applicant: ANTONINO CONTE ,  CARMELO UCCIARDELLO ,  CARMINE D'ALESSANDRO ,  MARIO MICCICHE ,  GIOVANNI MATRANGA ,  DIEGO DE COSTANTINI

Inventor： ANTONINO CONTE ,  CARMELO UCCIARDELLO ,  CARMINE D'ALESSANDRO ,  MARIO MICCICHE ,  GIOVANNI MATRANGA ,  DIEGO DE COSTANTINI

IPC: G05F1/10

CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C16/12 ,  H02M3/07

Abstract: A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.

Abstract translation: 提供一种电荷泵系统，其包括用于产生第一工作电压的至少一个第一泵，用于产生第二工作电压的第二泵和用于产生第三工作电压的第三泵。 第一泵连接到可以具有有限值的内部电源参考电压，并且具有连接到第二和第三泵的输出端，以便向它们提供第一工作电压作为它们的电源电压。 还提供了一种用于管理与这种电荷泵系统一起使用的电压的产生的方法。

公开(公告)号：US20080001662A1

公开(公告)日：2008-01-03

申请号：US11755711

申请日：2007-05-30

Applicant: Francesco Dalena

Inventor： Francesco Dalena

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F2200/456 ,  H03F2200/513 ,  H03F2203/45448 ,  H03F2203/45454 ,  H03F2203/45644 ,  H03F2203/45648

Abstract: A class AB operational amplifier is provided that includes first and second input transistors respectively coupled between first and second internal nodes and a first common node, first and second input stage load transistors diode connected and respectively coupled between a first voltage reference and the first and second internal nodes, first and second output transistors coupled in series between the first voltage reference and a second voltage reference, a tail current generator coupled between the first common node and the second voltage reference, an adaptive bias block coupled between the first and second voltage references and coupled to the first common node, and a positive feedback network coupled between the first voltage reference and the first and second internal nodes. Also provided is an integrated circuit having at least one such operational amplifier.

Abstract translation: 提供了一种AB类运算放大器，其包括分别耦合在第一和第二内部节点之间的第一和第二输入晶体管和第一公共节点，第一和第二输入级负载晶体管二极管连接并分别耦合在第一电压基准与第一和第二 内部节点，串联耦合在第一参考电压和第二电压基准之间的第一和第二输出晶体管，耦合在第一公共节点和第二电压基准之间的尾电流发生器，耦合在第一和第二电压基准之间的自适应偏置块 并耦合到第一公共节点，以及耦合在第一电压基准和第一和第二内部节点之间的正反馈网络。 还提供了具有至少一个这样的运算放大器的集成电路。

公开(公告)号：US20070296360A1

公开(公告)日：2007-12-27

申请号：US11735199

申请日：2007-04-13

Applicant: Marco Viti

Inventor： Marco Viti

IPC: H02P7/06 ,  H02P29/02

CPC classification number: H02P6/182

Abstract: A monitoring device for an electric motor has in input a signal representing zero crossings of the back-electromotive force of the motor and comprises a monitor that detects the signal in first periods of time arranged around instants of time in which the zero crossings are expected. The device comprises a setting circuit that sets second periods of time that are less than the first periods of time and each second period of time is centered on the instant of time in which the zero crossing is expected. The monitor comprises a detector that tests whether each actual zero crossing occurs inside the second period of time and a controller that modifies by a quantity the subsequent period of electric revolution time between two consecutive expected instants of zero crossing if said actual zero crossing occurs outside the second period of time.

Abstract translation: 用于电动机的监视装置输入表示电动机的反电动势的零交叉的信号，并且包括监视器，该监视器在预期为零交叉的时刻的时刻周围设置的第一时间段中检测信号。 设备包括设置电路，其设置小于第一时间段的第二时间段，并且每个第二时间段以期望过零的时刻为中心。 该监视器包括检测器，其检测每个实际过零点是否发生在第二时段内;以及控制器，如果所述实际过零点发生在 第二段时间。

公开(公告)号：US20070285999A1

公开(公告)日：2007-12-13

申请号：US11739167

申请日：2007-04-24

Applicant: Umberto Di Vincenzo ,  Roberto Versari ,  Massimiliano Mollichelli

Inventor： Umberto Di Vincenzo ,  Roberto Versari ,  Massimiliano Mollichelli

IPC: G11C5/14

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/063

Abstract: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through a respective bit line. The sensing circuit includes: an access circuit node adapted to be coupled to the bit line; precharging circuitry adapted to be activated in a precharge phase of the sensing operation preceding the evaluation phase, so as to bring a voltage of said access circuit node to a reference voltage; a reference circuit node coupled to the access circuit node and arranged to receive the reference current. The sensing circuit further includes an evaluation circuit node coupled to the reference circuit node through a first current to voltage converter, adapted to sink a current flowing from the reference circuit node to the evaluation circuit node and to produce a corresponding voltage difference between the reference circuit node and the evaluation circuit node, wherein the current is nearly equal to the reference current substantially at the end of the precharge phase; comparator circuitry is provided, adapted to compare the voltage of the access circuit node with the voltage of the evaluation circuit node and to provide a corresponding comparison signal whose time pattern indicates when the cell current exceeds the reference current. The first current to voltage converter is an electronic device having essentially the behavior of a diode.

Abstract translation: 提供感测电路。 感测电路适于确定在感测操作的评估阶段期间流过所选择的存储器单元的单元电流何时超过参考电流。 感测电路适于通过相应的位线耦合到至少一个选择的存储器单元。 感测电路包括：适于耦合到位线的接入电路节点; 预充电电路，其适于在所述评估阶段之前的所述感测操作的预充电阶段中被激活，以使所述访问电路节点的电压达到参考电压; 参考电路节点，其耦合到所述接入电路节点并被布置成接收所述参考电流。 感测电路还包括通过第一电流 - 电压转换器耦合到参考电路节点的评估电路节点，适于吸收从参考电路节点流向评估电路节点的电流，并产生参考电路之间的相应电压差 节点和评估电路节点，其中电流几乎等于基本上在预充电阶段结束时的参考电流; 提供比较器电路，用于将访问电路节点的电压与评估电路节点的电压进行比较，并提供对应的比较信号，其时间模式指示电池电流何时超过参考电流。 第一个电流到电压转换器是具有基本上二极管行为的电子器件。

公开(公告)号：US20070147477A1

公开(公告)日：2007-06-28

申请号：US11318052

申请日：2005-12-23

Applicant: Marco Cavallaro ,  Tino Copani ,  Giovanni Girlando ,  Giuseppe Palmisano

Inventor： Marco Cavallaro ,  Tino Copani ,  Giovanni Girlando ,  Giuseppe Palmisano

IPC: H04B1/00

CPC classification number: H04B1/71635 ,  H04B1/7174

Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.

Abstract translation: 提供脉冲发生器电路。 脉冲发生器电路具有适于接收输入电量的输入和输出电量可用的输出。 传输特性建立所述输入和所述输出电量之间的关系。 脉冲发生器电路适于提供具有预定形状的脉冲形式的所述输出电量，适合于用于UWB传输。 转印特性具有与所述脉冲基本相同的形状。 此外，提出了利用新型脉冲发生器的UWB调制系统。

公开(公告)号：US20070096072A1

公开(公告)日：2007-05-03

申请号：US11399297

申请日：2006-04-06

Applicant: Richard Dodge ,  Guy Wicker

Inventor： Richard Dodge ,  Guy Wicker

IPC: H01L29/02 ,  G11C11/00 ,  H01L21/302

CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/16

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract translation: 横向相变存储器包括由绝缘层隔开的一对电极。 第一电极形成在绝缘层的开口中并且是杯形的。 第一电极被绝缘层覆盖，绝缘层又被第二电极覆盖。 结果，电极之间的间隔可以被非常精确地控制并且被限制在非常小的尺寸。 在形成相变材料区域之前，电极有利地由相同的材料形成。

公开(公告)号：US20070071086A1

公开(公告)日：2007-03-29

申请号：US11534803

申请日：2006-09-25

Applicant: Edoardo Botti ,  Juri Cambieri

Inventor： Edoardo Botti ,  Juri Cambieri

IPC: H03K7/08

CPC classification number: H03F3/2171 ,  H03F2200/351

Abstract: A method for controlling a PWM power stage is based upon dampening current peaks generated by switching of the PWM power stage. The PWM power stage includes at least two MOS transistors of opposite conductivity coupled between an output node of the PWM power stage and respective positive and negative supply lines, and respective free-wheeling diodes. The method includes forming the at least two MOS transistors such that their reverse conduction threshold voltage is smaller than a sum between their forward conduction threshold voltage and a forward voltage on the respective free-wheeling diode at which a pre-established current flows therethrough. The at least two MOS transistors are in a high impedance state by biasing respective control nodes at a turn-off voltage such that their gate-source voltage is between the forward conduction threshold voltage and a null voltage.

Abstract translation: 用于控制PWM功率级的方法基于通过PWM功率级的切换产生的衰减电流峰值。 PWM功率级包括耦合在PWM功率级的输出节点和相应的正和负电源线之间的相反电导率的至少两个MOS晶体管和相应的续流二极管。 该方法包括形成至少两个MOS晶体管，使得它们的反向导通阈值电压小于其预先建立的电流流过其中的相应续流二极管的正向电压阈值电压和正向电压之和。 至少两个MOS晶体管处于高阻抗状态，通过以关断电压偏置各个控制节点，使得它们的栅极 - 源极电压在正向导通阈值电压和零电压之间。

公开(公告)号：US20070030730A1

公开(公告)日：2007-02-08

申请号：US11495886

申请日：2006-07-28

Applicant: Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

Inventor： Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

IPC: G11C16/06

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging a reading node associated with the selected memory cell with a charging voltage, means for biasing the selected memory cell with a biasing voltage, means for connecting the charged reading node with the biased selected memory cell, and means for sensing a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay, wherein for at least a second one of the reference voltages the biasing voltage is a second biasing voltage different from the second reference voltage, and the delay is a second delay different from the first delay.

Abstract translation: 提出了一种非易失性存储器件。 该非易失性存储器件包括多个具有可编程阈值电压的存储单元，以及用于针对每个所选择的存储器单元读取相对于多个参考电压的一组所选存储单元的装置，所述读取装置包括装置 用于利用充电电压对与所选择的存储器单元相关联的读取节点进行充电，用于利用偏置电压偏置所选择的存储单元的装置，用于将所述充电的读取节点与所偏置的选择的存储单元相连接的装置，以及用于感测所述存储单元 在来自所述连接的预定义延迟之后的读取节点，对于所述参考电压中的至少第一参考电压，所述偏置电压是等于所述第一参考电压的第一偏置电压，并且所述延迟是公共的第一延迟，其中对于至少第二个 的参考电压，偏置电压是与第二参考电压不同的第二偏置电压，并且延迟是第二延迟di 与第一次延迟不同。

公开(公告)号：US20060253763A1

公开(公告)日：2006-11-09

申请号：US11397330

申请日：2006-04-04

Applicant: Silvio Oliva ,  Gabriella Convertino

Inventor： Silvio Oliva ,  Gabriella Convertino

IPC: H04L1/00

CPC classification number: H04L1/0001 ,  H04L1/0009 ,  H04L1/0026 ,  H04L1/0057 ,  H04L1/0071

Abstract: The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments.

Abstract translation: 可以通过以下操作来校正由突发错误影响的通道上发送的数字数据中可能发生的错误：按每个包含确定数量的数据包的块排序数字数据; 为每个块生成包括相应数量的校正分组的相应组的纠错分组，所述相应数量标识用于校正所述错误的冗余级别; 以及根据突发的特性和两个突发之间的正确接收间隔动态修改冗余度。 优惠的应用在本地网络上，如在家庭环境中使用的W-LAN。