Abstract:
A transceiver for orthogonal frequency division multiplex communication has a transmitter module (1) and a receiver module (2). The transmitter (1) has an l-path (3) and a Q-path (4) to receive signals on a number of subcarriers provided by a signal generator (9). The receiver module (2) has a receiver l-path (7) and a receiver Q-path (8) to deliver signals to a processor (15). IQ imbalance is calculated for each of the transmitter and receiver by the signal generator sending a sample signal (Xl(k), XQ(k)) over a one of the transmitter paths. The signal is then applied to one or each of the inputs to the receiver paths (7,8) to generate receiver output signals Yl(k), YQ(k), RQ(k). The processor (15) is responsive to the output signals to calculate the transmitter and receiver IQ imbalance for that subcarrier. A calibrator (19) and compensator (20) are responsive to the calculated IQ imbalance to correct or compensate each subcarrier of the transceiver band.
Abstract:
The invention relates to a circuit (100) for use with a loudspeaker (104) having a first differential input terminal (t1) and a second differential input terminal (t2), the circuit (100) comprising: a differential power amplifier (103) having a first differential output terminal (t3) operatively connected to the first differential input terminal (t1) of the loudspeaker (104) and a second differential output terminal (t4) operatively connected to the second differential input terminal (t2) of the loudspeaker (104);—a first resistor (RS1) disposed between the first differential output terminal (t3) of the differential power amplifier (103) and the first differential input terminal (t1) of the loudspeaker (104); a second resistor (RS2) disposed between the second differential output terminal (t4) of the differential power amplifier (103) and the second differential input terminal (t2) of the loudspeaker (104). The circuit (100) further comprises: a first resistive module (RR1, RR2) arranged to generate on a respective output terminal (t5) a first control voltage (VIN), the first resistive module (RR1, RR2) having a first input terminal (t6) connected to the first differential output terminal (t3) of the power amplifier (103) and a second input terminal (t7) connected to the second differential input terminal (t2) of the loudspeaker (104), a second resistive module (RR3, RR4) arranged to generate on a respective output terminal (t8) a second control voltage (VIP), the second resistive module (RR3, RR4) having a first input terminal (t9) connected to the second differential output terminal (t4) of the power amplifier (103) and a second input terminal (t10) connected to the first differential input terminal (t1) of the loudspeaker (104). The loudspeaker circuit (100) being arranged to control the differential power amplifier (103) on the basis of the first control voltage (VIN) and the second control voltage (VIP).
Abstract:
An oscillator (200, 300, 350) comprises a tank circuit (100), a first transistor (M1c) and a second transistor (M1r), and the second transistor (M1r) occupies an area of silicon that is smaller than an area of silicon occupied by the first transistor (M1c). A switching apparatus (Sw1 . . . Sw14) selects either one of a first oscillator topology and a second oscillator topology, where in the first oscillator topology, the tank circuit (100) is coupled to the first transistor (M1c) in a first feedback configuration to provide feedback around the first transistor (M1c), and in the second oscillator topology, the tank circuit (100) is coupled to the second transistor (M1r) in a second feedback configuration that is different to the first feedback configuration to provide feedback around the second transistor (M1r).
Abstract:
An apparatus for calibrating a stereoscopic camera with respect to at least one stereo-image of the stereoscopic camera includes a processing unit configured to support at least a first triangulation unit, a second triangulation unit, and a Bundle Adjustment unit. The processing unit is configured to determine whether a convergence criterion has been met, the convergence criterion being indicative of whether or not a camera calibration ground-truth has been found.
Abstract:
The present subject matter discloses a system and a method for estimating a frequency offset in communication devices. In one embodiment, the method of estimating a frequency offset in a communication device comprises generating a reconstructed signal based at least in part on a channel impulse response (CIR) corresponding to a received signal. Further, a normalization matrix is determined for the reconstructed signal. Thereafter, based at least in part on the normalization matrix and the reconstructed signal, the frequency offset is estimated such that the frequency offset corresponds to a maximum normalized-correlation between the reconstructed signal and the received signal.
Abstract:
A method and an apparatus determine a time of start of series of OFDM symbols forming an OFDM packet, wherein one or more symbols of the OFDM signal includes a plurality of copies of a short training sequence made of a plurality of time-domain samples. The method includes determining a coarse time index, determining a fine time index, and determining the time of start of each OFDM symbols based on the fine time index. The coarse time-domain sample of the coarse time index is within a coarse estimation error interval, and the time-domain samples of the coarse estimation error interval are converted into frequency domain samples. A metric value is determined for each frequency domain samples, and the fine time index is the time index corresponding to one of the coarse estimation error interval having its associated frequency domain sample having the lowest metric value.
Abstract:
A voltage level shifting device for driving a capacitive load has an input terminal for receiving a first input signal switchable between a first logic state corresponding to a first reference voltage and a second logic state corresponding to a second reference voltage, and an output terminal for supplying an output signal switchable between a first logic state corresponding to a third reference voltage and a second logic state corresponding to a fourth reference voltage. The device also has a first electronic circuit that is activated following a commutation of the first input signal from the first reference voltage to the second reference voltage for fixing the output terminal to the fourth reference voltage. The device further has a second electronic circuit that is activated following a commutation of the first input signal from the second reference voltage to the first reference voltage.
Abstract:
An electronic analog-to-digital conversion device includes an analog-to-digital conversion block having a first input for receiving a voltage signal to be converted based on a reference voltage signal provided to a second input, and an input block connected to the first input of the analog-to-digital conversion block. The input block receives an input signal at a first resistive network connected to a second resistive network, which is then connected to a reference potential. The input block also includes an active network connected between an output of the first resistive network and the first input of the analog-to-digital conversion block. The active network has a first input terminal directly connected to the second input of the analog-to-digital conversion block for receiving the same reference voltage signal so that the input voltage signal received at a second input of the active network is processed based on the reference voltage signal.
Abstract:
A method of encoding video data including a sequence of digital image frames, in a pipelined processing system is provided. The method includes dividing each frame in the sequence into a plurality of sections, each section including a horizontal band across a frame. The method further includes subdividing each section into a plurality of macroblocks, and encoding a representation of each macroblock in each section to form an output stream. The sections of each frame are processed during adjacent steps in a pipeline of the pipelined processing system.
Abstract:
A receiver (100) has an ln-phase path (l-path) (101) that delivers a digital l-path signal x1(t) and a Quadrature path (Q-path) (103) that delivers a digital Q-path signal xQ(t). The receiver (100) includes a compensation stage (124) arranged to compensate for gain error g and phase error φ between the digital l-path signal x1(t) and the digital Q-path signal xQ(t). The compensation stage (124) has a compensation coefficient generation stage (200), a compensation coefficient application stage (202), a gain control stage (208), a relative gradient generation stage (214) and a step parameter generation stage (224). Compensation coefficients W1,1, W1,2, W2,1, W2,2 applied to the digital l-path signal x1(t) and the digital Q-path signal xQ(t) are generated by iteratively updating them using a relative gradient of the compensated digital in-phase signal y1(t) and a compensated digital quadrature signal yQ(t), and a step parameter μn, the magnitude of which is adjusted based on a rate of change of the compensation coefficients W1,1, W1,2, W2,1, W2,2.