公开(公告)号：US11691870B2

公开(公告)日：2023-07-04

申请号：US17164546

申请日：2021-02-01

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alessandro Tocchio ,  Lorenzo Corso

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/00246 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2207/092 ,  B81B2207/096 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0136 ,  B81C2203/0771 ,  B81C2203/0792

Abstract: An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

公开(公告)号：US20230208294A1

公开(公告)日：2023-06-29

申请号：US17560977

申请日：2021-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Aldo VIDONI ,  Andrea BARBIERI ,  Franco CONSIGLIERI

IPC: H02M3/158 ,  G02B26/08

CPC classification number: H02M3/158 ,  G02B26/0833

Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node at which a first output voltage is generated, and a second path coupled between the input node and a second output node at which a second output voltage is generated. The DC-DC boost converter operates in a first operating phase where the first path boosts the first output voltage and where the second path is kept from boosting the second output voltage by the second path being coupled to the first path, and operates in a second operating phase where the second path boosts the second output voltage and where the first path is kept from boosting the first output voltage by the second path not being coupled to the first path.

公开(公告)号：US11686673B2

公开(公告)日：2023-06-27

申请号：US17217662

申请日：2021-03-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Maria Eloisa Castagna ,  Salvatore Cascino ,  Viviana Cerantonio ,  Antonello Santangelo

IPC: G01N21/3504

CPC classification number: G01N21/3504

Abstract: The device is formed in a casing including a support, a spacer body, and a mirror element fixed together. A light-emitting element and a light-receiving element are arranged on a bearing surface of the support and face a reflecting surface of the mirror element. The light-emitting element is configured to generate infrared radiation, and the light-receiving element is configured to receive light radiation reflected by the reflecting surface. The spacer body has an emission opening housing the light-emitting element and a reception opening housing the light-receiving element; the reception opening comprises a radiation-limitation portion configured to enable entry of reflected light radiation having an angle, with respect to a normal to the bearing surface, of less than a preset value.

公开(公告)号：US20230194787A1

公开(公告)日：2023-06-22

申请号：US18167392

申请日：2023-02-10

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric BOEUF ,  Luca Maggi

IPC: G02B6/124 ,  G02B6/34 ,  G02B6/43 ,  G02B6/30 ,  G02B6/12 ,  G02B6/136

CPC classification number: G02B6/124 ,  G02B6/34 ,  G02B6/43 ,  G02B6/30 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12061

Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

公开(公告)号：US20230187425A1

公开(公告)日：2023-06-15

申请号：US18147563

申请日：2022-12-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Davide Giuseppe PATTI ,  Mario Antonio ALEO

IPC: H01L25/16 ,  H01L21/762 ,  H01L21/763 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/763 ,  H01L21/76224 ,  H01L25/50

Abstract: A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

公开(公告)号：US11676434B2

公开(公告)日：2023-06-13

申请号：US17198612

申请日：2021-03-11

Applicant: STMicroelectronics S.r.l.

Inventor： Carlo Cimino ,  Luca Di Cosmo

IPC: G07C9/22 ,  G06F21/35 ,  G07C9/00 ,  H04W4/80

CPC classification number: G07C9/22 ,  G06F21/35 ,  G07C9/00174 ,  G07C9/00309 ,  G06F2221/2103 ,  G06F2221/2111 ,  G07C2009/00341 ,  G07C2009/00769 ,  H04W4/80

Abstract: A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.

公开(公告)号：US11675720B2

公开(公告)日：2023-06-13

申请号：US17811209

申请日：2022-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

IPC: G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

CPC classification number: G06F13/287 ,  G06F9/467 ,  G06F13/37 ,  G06F13/372 ,  G06F17/142

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

公开(公告)号：US11673799B2

公开(公告)日：2023-06-13

申请号：US17155429

申请日：2021-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Enri Duqi ,  Nicolo′ Boni ,  Lorenzo Baldo ,  Massimiliano Merli ,  Roberto Carminati

IPC: B81C1/00 ,  H01L41/35

CPC classification number: B81C1/00158 ,  H01L41/35 ,  B81C2201/013

Abstract: To manufacture an oscillating structure, a wafer is processed by: forming torsional elastic elements; forming a mobile element connected to the torsional elastic elements; processing the first side of the wafer to form a mechanical reinforcement structure; and processing the second side of said wafer by steps of chemical etching, deposition of metal material, and/or deposition of piezoelectric material. Processing of the first side of the wafer is carried out prior to processing of the second side of the wafer so as not to damage possible sensitive structures formed on the first side of the wafer.

公开(公告)号：US20230179244A1

公开(公告)日：2023-06-08

申请号：US17457496

申请日：2021-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： Nunzio Spina ,  Giuseppe Palmisano ,  Alessandro Castorina

IPC: H04B1/16 ,  H03F3/19 ,  H04L27/06

CPC classification number: H04B1/16 ,  H03F3/19 ,  H04L27/06 ,  H03F2200/451

Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelop detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.

公开(公告)号：US11670685B2

公开(公告)日：2023-06-06

申请号：US17226003

申请日：2021-04-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone Rascuná ,  Paolo Badalá ,  Anna Bassi ,  Gabriele Bellocchi

IPC: H01L29/872 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L29/1606 ,  H01L29/6603 ,  H01L29/66143 ,  H01L29/872

Abstract: A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.