公开(公告)号：US20170062299A1

公开(公告)日：2017-03-02

申请号：US15050253

申请日：2016-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Laurent Marechal ,  Yvon Imbs ,  Laurent Schwarz

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01Q1/2283 ,  H01L21/3105 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/1815

Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.

Abstract translation: 电子设备包括具有安装面和电连接网络的支撑板。 集成电路芯片安装在安装面上并连接到电气连接网络。 封装块嵌入集成电路芯片。 由导电材料制成的附加元件至少部分地嵌入在封装块内。 附加导电元件具有平行于支撑板延伸的主要部分，并具有与集成电路芯片电连接的次级部分。 在密封块中形成开口，并且次级部分延伸到该开口中以形成电连接。 附加导电元件可以是天线。

公开(公告)号：US12212320B2

公开(公告)日：2025-01-28

申请号：US18296325

申请日：2023-04-05

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino Conte ,  Marco Ruta ,  Michelangelo Pisasale ,  Thomas Jouanneau

IPC: H03K19/20 ,  H03K19/0185

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

公开(公告)号：US12124815B2

公开(公告)日：2024-10-22

申请号：US17747101

申请日：2022-05-18

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Pierre Gobin ,  Jeremy Ribeiro De Freitas

IPC: G06F7/548 ,  G06F7/523 ,  G06F7/544

CPC classification number: G06F7/544 ,  G06F7/523

Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

公开(公告)号：US20240243712A1

公开(公告)日：2024-07-18

申请号：US18411748

申请日：2024-01-12

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL ,  Samuel FOULON

IPC: H03F3/45 ,  H03F1/32

CPC classification number: H03F3/45183 ,  H03F1/3205 ,  H03F3/45744

Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.

公开(公告)号：US20240231410A9

公开(公告)日：2024-07-11

申请号：US18379262

申请日：2023-10-12

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Julien GOULIER ,  Nicolas GOUX ,  Marc JOISSON

IPC: G05F3/26 ,  G05F1/46 ,  H03K17/18 ,  H03K17/22

CPC classification number: G05F3/262 ,  G05F1/468 ,  H03K17/18 ,  H03K17/22 ,  H03F3/45179

Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.

公开(公告)号：US12008244B2

公开(公告)日：2024-06-11

申请号：US17810093

申请日：2022-06-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.

公开(公告)号：US20240171424A1

公开(公告)日：2024-05-23

申请号：US18509618

申请日：2023-11-15

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics (Alps) SAS

Inventor： Fred Rennig ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Philippe Sirito-Olivier ,  Fritz Burkhardt ,  Aldo Occhipinti

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/40215

Abstract: A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.

公开(公告)号：US11988776B2

公开(公告)日：2024-05-21

申请号：US18359477

申请日：2023-07-26

Applicant: STMicroelectronics (Alps) SAS

Inventor： Romain David ,  Xavier Branca

IPC: G01S7/484 ,  G01S17/10 ,  H01S5/042 ,  H01S5/062

CPC classification number: G01S7/484 ,  G01S17/10 ,  H01S5/0428 ,  H01S5/062

Abstract: The present disclosure relates to a driver circuit for an optical light emitter of a ranging device, the driver circuit comprising: an inductor having a first of its nodes coupled to a current driver; a first branch comprising a first switch coupled between the second node of the inductor and a first supply voltage rail; a second branch for conducting a current through the optical light emitter, the second branch being coupled between the second node of the inductor and the first supply voltage rail; and a current sensor configured to detect the current passing through the inductor and to provide a feedback signal to the current driver.

公开(公告)号：US11907156B2

公开(公告)日：2024-02-20

申请号：US17457553

申请日：2021-12-03

Applicant: STMicroelectronics France ,  STMicroelectronics (Alps) SAS

Inventor： Michael Soulie ,  Thomas Martin

IPC: G06F15/78 ,  G06F1/08 ,  G06F1/14

CPC classification number: G06F15/7807 ,  G06F1/08 ,  G06F1/14

Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

公开(公告)号：US11876732B2

公开(公告)日：2024-01-16

申请号：US17100505

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Daniel Olson ,  Loic Pallardy ,  Nicolas Anquet

IPC: H04L41/0803 ,  H04L49/109 ,  G06F21/85

CPC classification number: H04L49/109 ,  G06F21/85 ,  H04L41/0803

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.