公开(公告)号：US20190355666A1

公开(公告)日：2019-11-21

申请号：US16510295

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/13 ,  H01L21/56 ,  H01L23/48 ,  H01L25/065

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10468367B2

公开(公告)日：2019-11-05

申请号：US15884167

申请日：2018-01-30

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US10380496B2

公开(公告)日：2019-08-13

申请号：US15925594

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Hubert C. George ,  Shawna M. Liff ,  James S. Clarke

IPC: G06N10/00 ,  B82Y10/00 ,  H01L29/12 ,  H01L23/00 ,  H01L29/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

公开(公告)号：US20190198965A1

公开(公告)日：2019-06-27

申请号：US16325522

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Richard J. Dischler ,  Johanna M. Swan

IPC: H01P11/00 ,  H01P3/12

CPC classification number: H01P11/002 ,  H01P3/122

Abstract: An apparatus comprises a waveguide section including an outer layer of conductive material tubular in shape and having multiple ends; and a joining feature on at least one of the ends of the waveguide section configured for joining to a second separate waveguide section.

公开(公告)号：US20190173149A1

公开(公告)日：2019-06-06

申请号：US16325301

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Sasha N. Oster ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/12 ,  H01P11/00 ,  H01P3/127 ,  H01P3/16

Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.

公开(公告)号：US10263312B2

公开(公告)日：2019-04-16

申请号：US15282050

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/12 ,  H01P3/16 ,  H01P11/00 ,  H01P3/14

Abstract: A method of making a waveguide ribbon that includes a plurality of waveguides comprises joining a first sheet of dielectric material to a first conductive sheet of conductive material, patterning the first sheet of dielectric material to form a plurality of dielectric waveguide cores on the first conductive sheet, and coating the dielectric waveguide cores with substantially the same conductive material as the conductive sheet to form the plurality of waveguides.

公开(公告)号：US10212827B2

公开(公告)日：2019-02-19

申请号：US15201323

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： John J. Browne ,  Andrew Maclean ,  Shawna M. Liff

IPC: H05K3/34 ,  H05K1/02 ,  G06F13/00 ,  H05K1/14

Abstract: Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.

公开(公告)号：US20190006572A1

公开(公告)日：2019-01-03

申请号：US15637682

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Ye Seul Nam ,  James S. Clarke ,  Jeanette M. Roberts ,  Roman Caudillo

IPC: H01L39/04 ,  H01L25/16 ,  H01L23/538 ,  H01L23/66 ,  H01L23/552 ,  H01L39/02 ,  H01L39/24 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  G06N99/00

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

公开(公告)号：US20170278816A1

公开(公告)日：2017-09-28

申请号：US15083089

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0133

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20170178990A1

公开(公告)日：2017-06-22

申请号：US14973184

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Srikant Nekkanty ,  Joshua D. Heppner ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Debendra Mallik ,  Shawna M. Liff ,  Yoko Sekihara

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L23/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/58

Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.