公开(公告)号：US20150187727A1

公开(公告)日：2015-07-02

申请号：US14643329

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract translation: 本公开涉及制造微电子封装的领域，其中在沉积在第一基板上的电介质层中形成空腔以保持焊接互连之间的分离。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中，并且在加热时可以形成焊料结构。 在其它实施例中，焊料结构可以放置在空腔中，或者可以形成在可以连接第一衬底的第二衬底上。 在其它实施例中，可以在第一基板和第二基板上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触焊盘或焊料结构的接触和回流来形成焊料互连。

公开(公告)号：US10468367B2

公开(公告)日：2019-11-05

申请号：US15884167

申请日：2018-01-30

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US20180151529A1

公开(公告)日：2018-05-31

申请号：US15884167

申请日：2018-01-30

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H05K1/18

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US20160148892A1

公开(公告)日：2016-05-26

申请号：US15009206

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US10794840B2

公开(公告)日：2020-10-06

申请号：US16473777

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Liang Zhang ,  Jianyong Mo ,  Darren A. Vance ,  Di Xu ,  Gregory S. Clemons ,  Robert F. Wiedmaier

IPC: G01N21/956 ,  G01N21/88 ,  G02B3/14 ,  G06T7/00 ,  H04N5/225

Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for package inspection. In some embodiments, the apparatus may include a light source to selectively project a first light defined by a first wavelength range to a surface of a package under inspection; an optical filter to selectively transmit, within a second wavelength range, a second light emitted by the surface of the package in response to the projection of the first light to the surface; a camera to generate one or more images of the surface, defined by the second light; and a controller coupled with the light source, optical filter, and camera, to process the one or more images, to detect a presence of a material of interest on the surface of the package, based at least in part on the first and second wavelength ranges. Other embodiments may be described and/or claimed.

公开(公告)号：US09530747B2

公开(公告)日：2016-12-27

申请号：US14643329

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.