公开(公告)号：US20200321347A1

公开(公告)日：2020-10-08

申请号：US16907858

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200312714A1

公开(公告)日：2020-10-01

申请号：US16902115

申请日：2020-06-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US10734272B2

公开(公告)日：2020-08-04

申请号：US15882821

申请日：2018-01-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/108 ,  H01L23/498 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L27/06

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20200013792A1

公开(公告)日：2020-01-09

申请号：US16578042

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/788 ,  H01L27/11524

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US20190371815A1

公开(公告)日：2019-12-05

申请号：US16437781

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/02

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US10483270B2

公开(公告)日：2019-11-19

申请号：US16270526

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190333934A1

公开(公告)日：2019-10-31

申请号：US16438334

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/66

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US10446566B2

公开(公告)日：2019-10-15

申请号：US15843509

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/115 ,  H01L29/78 ,  G11C16/04 ,  H01L27/11556 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/788 ,  H01L27/11524

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US20190198528A1

公开(公告)日：2019-06-27

申请号：US16290169

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76 ,  H01L29/7827

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20190189629A1

公开(公告)日：2019-06-20

申请号：US15843509

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  G11C16/08 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/788 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7883

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.