-
公开(公告)号：US08242761B2
公开(公告)日：2012-08-14
申请号：US12621273
申请日：2009-11-18
Applicant: Karel Napravnik
Inventor： Karel Napravnik
IPC: G05F1/00
CPC classification number: G05F1/575
Abstract: A low-dropout linear regulator includes an error amplifier comprising a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network for a loading current to flow therethrough. The regulator includes a current limiter inserted the flow-path of the loading current for the compensation network to increase the slew rate of the output of the differential amplifier by dispensing with the capacitive load in the frequency compensation network during load transients in the regulator.
Abstract translation: 低压差线性调节器包括误差放大器，该误差放大器包括差分放大器和增益级的级联布置，其间插入有用于流过其中的负载电流的频率补偿网络。 调节器包括限流器，其插入用于补偿网络的负载电流的流动路径，以通过在调节器中的负载瞬变期间分配频率补偿网络中的容性负载来增加差分放大器的输出的压摆率。
-
12.发明授权公开(公告)号：US08154265B2
公开(公告)日：2012-04-10
申请号：US12621181
申请日：2009-11-18
Applicant: Karel Napravnik
Inventor： Karel Napravnik
IPC: G05F1/40
CPC classification number: G05F1/575
Abstract: A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.
Abstract translation: 低压差线性稳压器包括误差放大器，其包括差分放大器和增益级的级联布置。 增益级包括由差分放大器驱动的晶体管，以在调节器的输出级的驱动信号处产生。 晶体管插在其源极 - 漏极线之间，包括在RC网络中的第一电阻负载，在调节器的开环增益中产生零，并产生第二电阻负载，以产生调节器的输出级的驱动信号。 第二阻性负载是非线性补偿元件，以使电流消耗线性地与调节器的负载电流成正比。 第一阻性负载是一个非线性元件，导致RC网络产生的零点频率随着调节器负载电流的减小而减小。
-
公开(公告)号：US20070170976A1
公开(公告)日：2007-07-26
申请号：US11655727
申请日：2007-01-19
Applicant: Hynek Saman , Peter Murin , Martin Boksa , Pavel Panus
Inventor： Hynek Saman , Peter Murin , Martin Boksa , Pavel Panus
IPC: H03K17/687
CPC classification number: H03F1/30 , H03F1/26 , H03F3/45475 , H03F3/45632 , H03F3/72 , H03F2200/372 , H03F2200/459 , H03F2203/45534
Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.
Abstract translation: 一种开关，包括第一晶体管，包括连接到第一开关节点的第一主端子，连接到第二开关节点的第二主端子和控制端子，所述第二开关节点连接到第一清洁电压源，以及第一控制电路 连接到第一晶体管的控制端子，包括连接到第一清洁电压源的第一节点，连接到第二电压电平的第二节点和控制输入节点，用于接收电源电压等级之间的第一输入控制信号变量 和第三电压电平，所述第一控制装置被布置成基于所述第一输入控制信号选择性地将所述第一晶体管的控制端子连接到所述第一节点和所述第二节点之一。
-
公开(公告)号：US12088429B2
公开(公告)日：2024-09-10
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , H03K7/08 , H04L12/40
CPC classification number: H04L12/403 , H03K7/08 , H04L12/40006 , H04L2012/40215
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
-
公开(公告)号：US20230300001A1
公开(公告)日：2023-09-21
申请号：US18174387
申请日：2023-02-24
Applicant: STMicroelectronics Application GMBH , STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. , STMicroelectronics S.r.l.
Inventor： Fred Rennig , Jochen Barthel , Ludek Beran , Mirko Dondini , Vaclav Dvorak , Vincenzo Polisi , Marianna Sanza' , CalogeroAndrea Trecarichi , Alfonso Furio
IPC: H04L12/40 , H03K19/00 , H03K17/687
CPC classification number: H04L12/40169 , H03K19/0002 , H03K17/6872 , H03K17/6874 , H04L12/40032 , H04L2012/40273 , H04L2012/40215
Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
-
Patent Agency Ranking
公开(公告)号：US11652457B2
公开(公告)日：2023-05-16
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor Petenyi
CPC classification number: H03F3/45179 , H03F1/0205 , H03F1/301 , H03F2200/78 , H03F2203/45
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
-
公开(公告)号：US11526458B2
公开(公告)日：2022-12-13
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
-
公开(公告)号：US20220159807A1
公开(公告)日：2022-05-19
申请号：US17523641
申请日：2021-11-10
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics Design and Application S.R.O.
Inventor： Donato TAGLIAVIA , Vincenzo POLISI , Calogero Andrea TRECARICHI , Francesco Nino MAMMOLITI , Jochen BARTHEL , Ludek BERAN
Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.
-
公开(公告)号：US20210367456A1
公开(公告)日：2021-11-25
申请号：US16878782
申请日：2020-05-20
Inventor： Michal Toula
Abstract: A wireless charging receiver includes a controller configured to determine that a first overvoltage threshold is met and based thereon enable a first switch to couple an output of a rectifier to electrical ground through a first resistor, to determine that a second overvoltage threshold is met and based thereon enable receive resonant circuit switches to short circuit a receive resonant circuit, to determine that a hysteresis threshold is met and based thereon disable the receive resonant circuit switches to open circuit the receive resonant circuit, and to determine that a hysteresis cycle threshold is met and that the receive resonant circuit switches are disabled and based thereon enable the second switch to couple the second resistor to the electrical ground and to communicate to wireless charging transmitter to decrease the power level on wireless charging receiver side.
-
公开(公告)号：US20210357344A1
公开(公告)日：2021-11-18
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
IPC: G06F13/362 , H04L12/40 , G06F11/07
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
-
-
-
-
-
-
-
-
-
Search Results
97
records
(took 0.026 seconds)
